Ph.D. Candidate - Analysis and improvement of fault tolerance and safety of AI accelerators - Contract Duration 3 Years (f/m/d)

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Feldkirchen, Bayern
Internship
Cloud • Hardware • Software • Semiconductor
The Role

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

In recent years, the adoption of Artificial Intelligence (AI) at the edge, particularly in the automotive industry, has grown exponentially. Edge AI, essential for Advanced Driver Assistance Systems (ADAS), enables real-time detection of road hazards, significantly enhancing driver safety. AI accelerators provide the computational power critical to these applications. As these accelerators become integral to automotive systems, ensuring their safety through robust safety mechanisms is crucial. In addition, tailored Electronic Design Automation (EDA) methodologies are essential for designing AI accelerators that meet the stringent safety standards required in the automotive industry.

This Ph.D. research focuses on enhancing the fault tolerance and safety of AI accelerators through innovative EDA methods. The research will involve analysing selected AI accelerators to assess their inherent fault tolerance and identify safety-critical components. The objective is to design hardware accelerators with advanced fault detection and correction mechanisms and to pinpoint areas requiring enhanced fault detection. This project will develop innovative methods to leverage EDA tool flows to efficiently detect and correct faults in AI accelerators. Additionally, existing Cadence tools and flows will be adapted to integrate AI capabilities. The developed concepts and methodologies will be demonstrated within the Cadence Functional Safety tool flow, applying them to real-world case studies.

Specific background:

  • M.Sc. (or equivalent) in Electrical Engineering, Computer Engineering, Computer Science, or related areas
  • Understanding of digital integrated circuit digital design & verification flows and tools
  • Knowledge of hardware design languages (Verilog, VHDL) and programming skills
  • Theoretical background in Functional Safety is preferred.

Requirements:

  • The applicant must fulfil the eligibility rules mentioned on the project website (https://tiramisu-project.eu/vacancies/eligibility) and the Ph.D. requirements of the Politecnico di Torino, where the candidate will be enrolled for Ph.D. studies.
  • An English language certificate (IELTS: minimum score 5.5, or one of the language certificates in substitution, e.g., Pearson, ETS, Cambridge English Language Assessment)

Note: This PhD project is part of the TIRAMISU European HORIZON MSCA Doctoral Network. The application for DC2.3 must also be submitted via the TIRAMISU website: https://tiramisu-project.eu/vacancies/application-procedure

Benefits we offer you:

  • Competitive Salary
  • 30 days annual leave
  • Meal vouchers
  • Capital Forming Payment (VwL)
  • Ticket for the public transport
  • Working in a hybrid model in a modern office concept

And so much more, do not hesitate to contact us.

We’re doing work that matters. Help us solve what others can’t.

The Company
HQ: San Jose, CA
8,216 Employees
On-site Workplace
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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