PDK Engineer

Job Details:

Job Description: 

• Develops, maintains, and ensures quality assurance of process design kit (PDK) collateral, including PDK runset, PDK extraction, and modeling transistors for Intel design teams to enable new processes and methodologies to be followed across Intel's product lines.
• Develops automation of QA flow methodologies for specific technology nodes to scale up QA coverage.
• Documents and monitors QA results. May include developing test patterns to quality the physical design rules for correct implementations.
• Performs validation for PDK library covering collaterals, partition cells, 3DIC packaging, and back end physical design checks.
• Ensures that the design teams meet the requirements of the process node. Leads root cause analysis for issues related to designing to a specific process technology and continuously drives initiatives to enhance design methodologies.
• Creates and maintains technology files with symbols, device parameters, Pcells, design verification decks, layouts, process constraints, design rule checks, and/or layout versus schematic runsets for silicon designers to understand the design process.
• Resolves issues and bugs found within the PDK collateral. Builds test structures and runs simulation, physical verification, and parasitic extraction to ensure proper model and design solutions.
• May also deliver design flows, guidelines, and tutorials through sample design databases, test chips, and libraries.
• Collaborate with silicon design, process engineering, and high volume manufacturing teams to identify new process technologies and ensure new solutions are high quality and ensure ease of use for both internal and external design communities.
• Works with EDA vendors on tool improvements to enhance performance and add functionality.

Qualifications:

• B.E./B.Tech/M.Tech with 7-10 years of relevant experience in custom layout design methodology and leading a team.
• Must have working knowledge on and custom compiler and virtuoso platform.
•  Must have good understanding of custom compiler and virtuoso technology files and its functionality.
• Must have hands-on experience in mask design and basic understanding of front end simulation process and tools.
• Candidate should be good in automation using Cadence SKILL/tcl/perl/python and other scripting languages.
• Candidate should be flexible to work on different aspects of PDK deliverables.
• Good in written and verbal communication skills.

Job Type:Experienced Hire

Shift:Shift 1 (India)

Primary Location: India, Bangalore

Additional Locations:

Business group:As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.