Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal and/or highspeed IPs required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods for mixed signal designs including analog behavior modeling and circuit simulation to write RTL and optimize mixed signal logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high quality integration of the IP block.
Qualifications:Minimum Qualifications:
- Bachelors with 4+ years of experience or master's with 3+ years of experience or PhD with 1+ years of experience in Computer Science or Computer Engineering or Electrical Engineering or related technical discipline
2+ years of experience with the following technical skills:
- Proficiency in RTL design and coding using System Verilog and Verilog.
- Expertise in mixed signal fundamentals, low-power design using UPF, and clock gating.
- Deep understanding of digital and analog design principles, clock domain crossing, and power-performance tradeoffs.
- Experience with hardware simulation tools and methodologies (VCS/Verdi). - Familiarity with IP environment and configuration management tools
- Experience with Front End design tools for Lint, CDC, RDC, Voltage Domain Crossings, Synthesis, Low power design.
This position is not eligible for an intel immigration sponsorship.
Preferred Qualifications:
- Demonstrated ability to debug complex logic designs, speed paths and validate system-level functionality.
- Ability to collaborate across diverse teams, mentor junior engineers, and contribute to a dynamic team environment.
- Strong problem-solving skills, disciplined execution, and a proactive mindset.
- DDR Design domain knowledge with good hold on DFI/DDR/LPDDR protocols
- VSCode GitHub CoPilot or any other AI experience.- Exposed to Formal Property Verification and Git version control
- Ability to drive an optimal solution between analog and digital designs
- Familiarity with pre-silicon and post-silicon validation.
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, California, FolsomAdditional Locations:US, California, San Jose, US, California, Santa ClaraPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- Bachelors with 4+ years experience or master's with 3+ years experience or PhD with 1+ years experience in relevant discipline
- 2+ years experience in RTL design and coding using System Verilog and Verilog
- Expertise in mixed signal fundamentals and low-power design using UPF
- Understanding of digital and analog design principles and power-performance tradeoffs
- Experience with hardware simulation tools and methodologies
- Familiarity with front end design tools for Lint, CDC, RDC
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
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Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
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Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
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Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
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