As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of high-speed and mixed signal IP designs at Intel. Your contributions will directly impact the development of cutting-edge technologies that enable the integration of functional units, IP blocks, and subsystems into full chip designs. This position is at the forefront of innovation, requiring collaboration with cross-functional teams to define architecture and microarchitecture features, optimize performance, and ensure design integrity. Your work will drive Intel's success in achieving power, performance, and area goals, empowering our customers with industry-leading solutions.
The primary responsibilities for this role will include, but are not limited to:
- Develop architecture and microarchitecture specifications for the logic components and contribute to the overall system architecture decisions
- Implement specifications/designs in RTL and coordinate the work of other junior designers to deliver high-quality, complex logic blocks
- Develop behavioral models that represent analog and mixed-signal circuit blocks using SystemVerilog
- Run simulations and debug using logic, mixed-signal validation, and AMS simulation tools
- Ensure high-quality designs by using industry standard tools such as linting and CDC analysis
- Support the physical design team in implementing your designs, including synthesis and timing closure
- Work with the pre-silicon validation/verification team to develop test plans and verification collateral
- Work with post-silicon validation teams to resolve post-silicon issues
A successful candidate will have proven experience demonstrating the following skills and behavioral traits:
- Comfortable working with a high level of independence.
Minimum Qualifications:
Minimum qualifications are required to be initially considered for this position.
Knowledge and/or experience listed below would be obtained through a combination of your school, work and/or classes and/or research and/or relevant previous job and/or internship experiences.
- BS degree in Electrical Engineering or Computer Engineering or similar field of study with 4+ years relevant experience -OR- MS degree in Electrical Engineering or Computer Engineering or similar field of study with 3+ years relevant experience.
- +3 years of experience:
- With standard digital design concepts such as FSM design techniques
- With SystemVerilog
- With computer architecture, analog design, ADC/DAC designs, communications theory, and/or microarchitecture design concepts
- With multiple clock-domain design
Preferred Qualifications:
Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
- BS degree in Electrical Engineering or Computer Engineering or similar field of study with 7+ years relevant experience OR- MS degree in Electrical Engineering or Computer Engineering or similar field of study with 5+ years relevant experience.
- Able to work highly independently, guide other junior team members and make contributions that increase the productivity of the entire design team
- Excellent communication and interpersonal skills
- Experience with both logic and analog circuits as well as with analog behavioral modeling
- Knowledge of mixed-signal validation, signal, and systems analysis
- Knowledge of High-Speed I/O protocol stacks (UCIe, PCIe, USB, etc.)
- Experience with scripting languages e.g. Perl, bash/csh and Python is highly desirable
- Experience mentoring junior designers to deliver quality designs
- Experience using RTL quality tools such as linting and CDC analysis and supporting team adoption and usage
- Experience with low-power design, power gating, and multiple power-domain design
- Experience with writing, testing, packaging, and releasing firmware
- Experience writing, testing, and supporting front-end automation and packaging flows
- Experience using AI tools as a productivity booster in all aspects of the IP design process
- Strong analytical debugging skills, with a creative approach to problem-solving
Join us in redefining technology and engineering challenges. Apply today and become part of a team where your expertise drives meaningful change and innovation.
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, Arizona, Phoenix, US, California, Santa ClaraBusiness group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-200,340.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- BS in Electrical Engineering or Computer Engineering (or similar) with 4+ years relevant experience OR MS with 3+ years relevant experience
- 3+ years experience with standard digital design concepts such as FSM design techniques
- 3+ years experience with SystemVerilog
- 3+ years experience with computer architecture, analog design, ADC/DAC designs, communications theory, and/or microarchitecture design concepts
- 3+ years experience with multiple clock-domain design
- Experience with both logic and analog circuits and analog behavioral modeling
- Knowledge of mixed-signal validation, signal and systems analysis
- Knowledge of High-Speed I/O protocol stacks (UCIe, PCIe, USB)
- Experience with scripting languages (Perl, bash/csh, Python)
- Experience using RTL quality tools such as linting and CDC analysis
- Experience with low-power design, power gating, and multiple power-domain design
- Experience writing, testing, packaging, and releasing firmware
- Experience with front-end automation and packaging flows
- Experience mentoring junior designers and working independently
- Strong analytical debugging skills and creative problem-solving
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
-
Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
-
Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
-
Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
Intel Insights
What We Do
Our mission is to shape the future of technology to help create a better future for the entire world, that’s the power of Intel Inside. With more ingenuity and creativity inside, our work is at the heart of countless innovations. From major breakthroughs to things that make everyday life better— they’re all powered by Intel technology. With a career at Intel, you can help make the future more wonderful for everyone.
