Memory Senior Layout Engineer

Mixel Vietnam is an innovator of high-performance analog mixed-signal semiconductor IPs, powering Mobile, Display, Camera, Automotive, VR, AR, and AI applications. As a member of Mixel Group and part of Silvaco Group (USA, NASDAQ: SVCO), we bring together the agility of a focused IP house with the scale, technology, and global reach of a leading EDA and semiconductor IP provider. 

Our mission is to deliver outstanding, silicon-proven mixed-signal IPs that give our customers and partners a clear technology advantage. We invest in our people the same way we invest in our IPs — with discipline, care, and a long-term view. 

At Mixel Vietnam you will find an environment built on technical excellence, employee well-being, minimal management layers, and the freedom to make meaningful contributions. We value open communication, empathy, mutual trust, and respect. 

Technical Execution & Innovation 

• Own the layout design and verification of critical memory IP blocks, including floorplanning, placement, routing, and signoff. 

• Develop custom layouts from schematics, including leaf-cell layout and re-floorplanning for compiler porting, optimizing area under tight constraints. 

• Optimize floorplan, routing, and power distribution to reduce parasitic and IR drop; perform EMIR analysis to resolve electromigration and IR-drop issues to clean sign-off. 

• Execute the full physical-verification flow (DRC, LVS, ERC/VERC, antenna, ResCheck/CapCheck, DFM) and resolve complex multi-level violations under tight schedules. 

• Implement and update ECOs for device and connectivity changes, and drive them through to clean re-verification. 

• Troubleshoot and resolve layout issues, driving technical solutions and improvements. 

• Own the physical implementation of a complete memory instance or compiler sub-family, including its floorplan strategy, quality criteria, and release. 

Quality, Automation & Methodology 

• Develop and implement automation scripts (Perl/Python/TCL/Shell/SKILL) to accelerate layout cycles and improve quality. 

• Follow and contribute to the design checklists, review gates, and sign-off criteria used by the Memory team, and generate the required documentation for release. 

• Conduct technical reviews and benchmarking of layout deliverables. 

• Introduce and implement methodology improvements that enhance layout quality and overall team efficiency. 

Collaboration & Support 

• Work in close cooperation with Memory Design, Modeling, DFT, Physical Design, and CAD teams to deliver on time and according to required specifications. 

• Provide technical input on project planning and risk assessment, and collaborate with layout leads, CAD, and process teams to optimize layout flows and methodologies. 

• Contribute to the validation and debugging of fabricated silicon. 

• Provide mentorship and technical guidance to junior layout engineers and interns. 

Essential Requirements 

• BS/MS in Electronics Engineering, Telecommunications, Microelectronics, Computer Engineering, Physics, or a related field. 

• Minimum 4 years of hands-on custom layout design experience for IC or IP development

• Proficient with layout capture tools (Cadence Virtuoso or equivalent). 

• Proficient with layout verification and extraction tools (Calibre, ICV, StarRC or equivalent). 

• Experience with parasitic extraction, post-layout impact analysis, and basic EMIR / IR-drop analysis. 

• Familiarity with advanced process nodes (e.g., 5nm, 3nm) and associated challenges. 

• Scripting skills (Perl, Python, TCL, or Shell) on Unix/Linux. 

• Excellent attention to detail and ability to work in a fast-paced, collaborative environment. 

• English Language Proficiency: Fluency, written and verbal. 

• Strong communication, analytical, and problem-solving skills. 

Desirable Requirements 

• Direct experience on memory IP layout (SRAM, DPRAM, ROM, Register File, or TCAM)

• Hands-on experience with memory compilers, porting, and view-generation flows. 

• Understanding of memory architectures (SRAM/ROM/Register File) and of pitch-matched leaf-cell design. 

• Familiarity with standard views (LEF, GDS, CDL). 

• Master’s degree in Electronics / Microelectronics Engineering. 

• Experience with advanced FinFET process nodes. 

• Knowledge of functional safety (ISO 26262) and quality (ISO 9001) processes.