Jobs at Silvaco Inc

Lead end-to-end design, tapeout, bring-up, and silicon validation of test chips to characterize and qualify standard cell libraries and memory compilers. Define architecture, implement physical design, develop ATE/bench test programs, run silicon bring-up, analyze measurements versus models, author silicon reports, and coordinate cross-functional stakeholders and foundries.

Lead end-to-end design, tapeout, and silicon validation of test chips for standard cell libraries and memory compilers. Define architecture and on-chip test structures, perform full physical implementation and signoff, develop ATE/bench test programs and DFT, lead silicon bring-up and debugging, analyze silicon vs pre-silicon models, author silicon reports, and manage schedule, budget, and stakeholders.

Develop, test, and maintain TCAD simulation software and a library of linear solvers. Improve numerical methods for PDEs, implement CPU/GPU parallelism (threads, MPI, CUDA), and document and present results while collaborating within a software team.

Lead the architecture and design of embedded memory compilers. Manage a design team, engage with customers, and ensure performance and integration of SRAM, ROM, and dual-port memories.

The role involves managing accounts receivable, performing reconciliations, assisting in month-end close activities, and improving accounting processes.

The role involves providing technical support for EDA tools and IPs, mentoring engineers, enhancing tool capabilities, and working with customers and sales to drive business growth.

Ensure effective operation of People systems, improve workflows, integrate tools, maintain data integrity, and provide training and support for users.

The Digital Design Engineer will develop design specifications, code in Verilog, conduct verification and timing analysis, and collaborate with design teams on testing digital modules.

Develop verification test plans, maintain UVM-based testbenches, execute RTL simulations, and support FPGA prototyping at Mixel.

Lead hands-on layout design, verification, and optimization for advanced memory IPs. Own floorplanning, placement, routing, signoff, troubleshooting, automation scripting, technical reviews, and collaborate with CAD and process teams to deliver high-quality layouts.

Lead and execute hands-on layout design for advanced memory IPs, oversee floorplanning, placement, routing, verification (DRC/LVS), automation development, mentor engineers, collaborate cross-functionally, and support tape-out and signoff.