Jobs at Silvaco Inc

Lead Workday configuration, integrations, and HRIS operations. Translate business needs into system requirements, build integrations and reports, perform audits, manage change, train users, and maintain data integrity while partnering cross-functionally to scale HR systems.

Support global compensation programs, job architecture, workforce analytics, and organizational design. Perform market pricing, salary structure maintenance, workforce reporting, dashboarding, survey management, and provide compensation recommendations to support executive decision-making and HR/Finance partners.

Provide operational HR support across the employee lifecycle: onboarding/offboarding, HR records, payroll and benefits administration, HRIS transactions, compliance reporting, EOR administration, HR audits, metrics tracking, and employee service support while partnering with HRBPs, TA, and HRIS teams to deliver consistent global HR operations.

Lead architecture, circuit design, and silicon validation of embedded memory compilers (SRAM, ROM, 1PRF/2PRF, DPRAM). Drive PPA, reliability, verification/signoff, team growth, presales/customer technical engagement, benchmarking, and foundry interaction across multiple process nodes and compiler variants.

Provide full-cycle HR generalist support for EMEA from Kyiv: advise managers, administer policies, manage performance and compensation processes, maintain HRIS and records, ensure legal compliance, support employee relations and HR projects.

Lead end-to-end design, tapeout, bring-up, and silicon validation of test chips to characterize and qualify standard cell libraries and memory compilers. Define architecture, implement physical design, develop ATE/bench test programs, run silicon bring-up, analyze measurements versus models, author silicon reports, and coordinate cross-functional stakeholders and foundries.

Develop, test, and maintain TCAD simulation software and a library of linear solvers. Improve numerical methods for PDEs, implement CPU/GPU parallelism (threads, MPI, CUDA), and document and present results while collaborating within a software team.

Lead and execute analog/mixed-signal implementation from specification through tape-out. Collaborate with digital, verification, and physical design teams; conduct design reviews; perform post-silicon validation, characterization, debugging, and root-cause analysis; identify risks and estimate effort; and drive process and tool improvements to meet performance, power, quality, and schedule goals.

Lead global technical recruiting strategy and full-cycle hiring for senior engineering roles. Partner with business leaders on workforce planning, build proactive sourcing pipelines, manage vendors, drive diversity and candidate experience, track recruiting metrics, mentor recruiters, and support strategic hiring projects.

Generate, validate, and deliver memory models and views (Liberty, Verilog) for SRAM/ROM/Register Files; verify models, debug mismatches, create DFT/Tessent descriptions and ATPG flows (TetraMAX, FastScan); automate model-generation and QA flows with scripting; collaborate with design, DFT, PD, and STA teams; mentor junior engineers.

Lead hands-on layout design and verification for advanced memory IPs including floorplanning, placement, routing, and signoff. Troubleshoot layout issues, create automation scripts to speed cycles, conduct technical reviews and benchmarking, and collaborate with CAD, process, and layout leads on planning and optimization.

Lead end-to-end design, tapeout, and silicon validation of test chips for standard cell libraries and memory compilers. Define test architecture and on-chip structures, perform full physical implementation and signoff flows, develop ATE/bench test programs and DFT, drive first-silicon bring-up and measurement campaigns, analyze correlation to pre-silicon models, author silicon reports, and coordinate cross-functional teams.

Perform accounts receivable tasks including aging monitoring, collections follow-up, AR reconciliations, and month-end close support. Assist with general accounting: reconciliations, accruals, GL and prepaid accounts, fixed asset tracking, intercompany postings, Concur report review, audit support, process improvements, and ad hoc reporting.

Three-month internship to learn from experienced engineers and contribute to real analog/mixed-signal semiconductor projects. Interns will develop practical skills using industry design methodologies and tools. Requires basic analog design knowledge; shell scripting and Unix/Linux skills are desirable. Outstanding interns may be considered for full-time roles.

Design and verify digital IP: write Verilog RTL, run synthesis and STA, develop verification environments (including FPGA and gate-level verification), perform CDC/RDC linting and formal checks, and support DFT and timing closure with physical design teams.

Three-month internship to learn digital verification using Verilog/SystemVerilog and UVM, contribute to real projects, work with coverage metrics and Unix/Linux tools, and gain exposure to RTL, synthesis, CDC analysis and scripting.

Three-month internship to learn from experienced engineers and contribute to real digital design projects. Work on Verilog RTL design/simulation, CDC/RDC techniques, ASIC/FPGA flows (RTL synthesis, place-and-route, timing sign-off), static timing analysis, and timing constraints (SDC) using industry tools and methodologies.

Lead micro-architecture specification, RTL design and verification of digital IPs. Manage and mentor teams, direct projects from spec to silicon, own schedules and risk, drive verification (UVM, SystemVerilog), perform FPGA-based hardware verification, engage customers, and define best practices to improve productivity and quality.

Three-month on-site internship to learn and contribute to custom analog IC layout projects. Interns will develop practical skills in industry-standard design methodologies, work with experienced engineers, and apply basic analog design and layout techniques. Strong emphasis on learning Shell scripting and Unix/Linux workflows; outstanding interns may be considered for full-time roles.

Design and implement system-level verification environments and UVM-based testbenches. Create constrained-random stimulus, monitors, scoreboards, and coverage models in SystemVerilog. Drive coverage closure, integrate VIPs, support FPGA prototyping and pre-silicon validation, run RTL/gate simulations, and contribute to regression, CI flows, and verification automation.