Jobs at Silvaco Inc

Develops, validates, and maintains SRAM, ROM, and register-file memory views and models, including Liberty timing/power models and behavioral Verilog/SystemVerilog models. Builds verification regressions, Tessent MBIST descriptions, TetraMAX ATPG patterns, and FastScan flows. Automates model-generation and QA processes using Perl, Python, TCL, and Shell on Unix/Linux. Collaborates with design, DFT, physical design, and STA teams, supports silicon validation, documents deliverables, and mentors junior engineers.

Leads the memory layout team and owns resource planning, development, recruiting, methodology, and technical quality. Remains hands-on in floorplanning, placement, routing, physical verification, parasitic extraction, EMIR, reliability closure, and tape-out of SRAM, ROM, DPRAM, register file, and related memory IP. Develops automation scripts and layout standards, drives process-node porting, resolves signoff issues, and collaborates with design, CAD, foundry, and global stakeholders.

Owns custom layout design and physical verification for critical memory IP, including floorplanning, placement, routing, extraction, EMIR analysis, ECO implementation, and signoff. Develops automation scripts, improves layout methodologies, supports silicon validation, and mentors junior engineers. Collaborates with memory design, modeling, DFT, physical design, CAD, and process teams to deliver complete memory instances or compiler sub-families.

Develops, validates, and maintains SRAM, ROM, and register-file memory views and models, including Liberty timing and power models and behavioral Verilog/SystemVerilog models. Builds verification and regression environments, debugs model mismatches, and supports Tessent, TetraMAX, and FastScan DFT flows. Automates generation and quality-assurance processes using scripting languages, collaborates with design and CAD teams, supports silicon validation, documents deliverables, and mentors junior engineers.

Handles accounts receivable monitoring, collections follow-up, reconciliations, month-end close, journal entries, general ledger maintenance, fixed assets, intercompany transactions, audit support, reporting, and accounting process improvements.

Design and own transistor-level memory circuit blocks, including decoders, drivers, sense amplifiers, control logic, and I/O. Run PVT, post-layout, Monte Carlo, margin, leakage, and retention analysis; resolve parasitic and EMIR issues; and support compiler development, ECOs, characterization, and silicon correlation. Develop automation scripts, define verification strategies, document results, collaborate across physical design teams, participate in reviews, and mentor junior engineers.

Lead end-to-end design, tapeout, bring-up, and silicon validation of test chips to characterize and qualify standard cell libraries and memory compilers. Define architecture, implement physical design, develop ATE/bench test programs, run silicon bring-up, analyze measurements versus models, author silicon reports, and coordinate cross-functional stakeholders and foundries.

Lead and execute analog/mixed-signal implementation from specification through tape-out. Collaborate with digital, verification, and physical design teams; conduct design reviews; perform post-silicon validation, characterization, debugging, and root-cause analysis; identify risks and estimate effort; and drive process and tool improvements to meet performance, power, quality, and schedule goals.

Lead global technical recruiting strategy and full-cycle hiring for senior engineering roles. Partner with business leaders on workforce planning, build proactive sourcing pipelines, manage vendors, drive diversity and candidate experience, track recruiting metrics, mentor recruiters, and support strategic hiring projects.

Develop, test, and maintain TCAD simulation software and a library of linear solvers. Improve numerical methods for PDEs, implement CPU/GPU parallelism (threads, MPI, CUDA), and document and present results while collaborating within a software team.

Lead architecture, circuit, and physical design of embedded memory compilers (SRAM, ROM, RF, DPRAM). Manage a team, drive PPA optimization, presales/customer engagements, silicon validation, and roadmap. Own verification, SPICE characterization, DFT/DFX, and foundry interfacing.

Lead architecture, circuit and physical implementation of embedded memory compilers (SRAM, ROM, register files, DPRAM). Own technical roadmap, PPA benchmarking, silicon validation, customer presales/support, and manage a team of memory designers across nodes and flows.

Lead end-to-end design, tapeout, and silicon validation of test chips for standard cell libraries and memory compilers. Define test architecture and on-chip structures, perform full physical implementation and signoff flows, develop ATE/bench test programs and DFT, drive first-silicon bring-up and measurement campaigns, analyze correlation to pre-silicon models, author silicon reports, and coordinate cross-functional teams.

Support global compensation programs, salary structure and survey analysis, workforce analytics, job architecture and leveling, organizational design, and executive reporting. Prepare compensation recommendations, manage incentive administration, collaborate with HR partners and finance, and ensure data accuracy and governance.

Support global compensation programs, salary structure maintenance, compensation benchmarking, workforce analytics, job architecture and career frameworks. Develop dashboards and reports, manage compensation surveys, support equity and long-term incentive administration, and assist organizational redesign in collaboration with HR business partners and Finance.

Design and implement system-level verification environments and UVM-based testbenches. Create constrained-random stimulus, monitors, scoreboards, and coverage models in SystemVerilog. Drive coverage closure, integrate VIPs, support FPGA prototyping and pre-silicon validation, run RTL/gate simulations, and contribute to regression, CI flows, and verification automation.

Lead micro-architecture specification, RTL design and verification of digital IPs. Manage and mentor teams, direct projects from spec to silicon, own schedules and risk, drive verification (UVM, SystemVerilog), perform FPGA-based hardware verification, engage customers, and define best practices to improve productivity and quality.

Three-month internship to learn from experienced engineers and contribute to real analog/mixed-signal semiconductor projects. Interns will develop practical skills using industry design methodologies and tools. Requires basic analog design knowledge; shell scripting and Unix/Linux skills are desirable. Outstanding interns may be considered for full-time roles.

Design and verify digital IP: write Verilog RTL, run synthesis and STA, develop verification environments (including FPGA and gate-level verification), perform CDC/RDC linting and formal checks, and support DFT and timing closure with physical design teams.

Three-month internship to learn from experienced engineers and contribute to real digital design projects. Work on Verilog RTL design/simulation, CDC/RDC techniques, ASIC/FPGA flows (RTL synthesis, place-and-route, timing sign-off), static timing analysis, and timing constraints (SDC) using industry tools and methodologies.