Memory Layout Design Engineer

Posted 12 Days Ago
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Hiring Remotely in Electronics City, Bangalore, Karnataka, IND
Remote
Mid level
Software • Semiconductor • Manufacturing
The Role
Design and deliver memory physical layouts for advanced CMOS processes using Cadence tools and Calibre/Hercules verification. Manage floor-planning, hierarchy, chip integration, schedule, and documentation. Lead reviews, mentor juniors, and ensure layouts meet DRC/LVS/ERC/antenna/electromigration and power/signal RC requirements.
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Job Description:

Job Requirements:
  - Minimum 3 years of experience with strong layout knowledge.
  - Bachelor's degree required.
  - Proficiency in using Cadence tools (Virtuoso Layout, Layout XL, Cadence Schematic Capture, and verification tools - CALIBRE & Hercules).
  - Strong layout knowledge in submicron processes (e.g., A14, 2nm, 3nm, 5nm, 7nm).
  - Experience in digital layout (Standard cell, Memory, I/O); analog layout experience is a plus.
Job Description:
  - Understand and apply layout guidelines, new process rules, and technical requirements for good quality layout.
  - Manage scheduling, timelines, and layout floor-planning.
  - Responsible for start-to-end deliverables with quality within the planned schedule.
  - Adapt quickly to new methodologies, remain open to new ideas, and communicate effectively with the SOC/library team.
Skill Set (Memory):
  - Strong experience in Memory layout design and physical verification (LVS, DRC, ERC, Antenna, ElectroMigration) in CMOS processes.
  - Experience with Cadence Layout tools (VIRTUOSO XL, VXL, or EXL) and CALIBRE verification tools.
  - Proficiency in floor-planning, hierarchy layout, and chip integration.
  - Understanding of memory architecture, RC requirements, and the ability to plan signal and power based on layout guidelines.
  - Knowledge of AI, automation in layout, Script Programming, and SKILL Programming is a plus.
  - Ability to lead, train junior engineers, and manage projects effectively.
  - Good knowledge of memory layout topology; experience with memory compilers is a plus.
  - Ability to lead new technology reviews to document layout methodologies, flows, and guidelines.
  - Self-reliant with the ability to work both independently and collaboratively.

Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Skills Required

  • Minimum 3 years of experience with strong layout knowledge
  • Bachelor's degree
  • Proficiency with Cadence tools (Virtuoso Layout, Layout XL, Cadence Schematic Capture)
  • Experience with verification tools CALIBRE and Hercules
  • Strong layout knowledge in submicron processes (A14, 2nm, 3nm, 5nm, 7nm)
  • Experience in digital layout (Standard cell, Memory, I/O); analog layout experience is a plus
  • Strong experience in Memory layout design and physical verification (LVS, DRC, ERC, Antenna, Electromigration) in CMOS processes
  • Proficiency in floor-planning, hierarchy layout, and chip integration
  • Understanding of memory architecture, RC requirements, and planning signal and power based on layout guidelines
  • Ability to lead, train junior engineers, and manage projects effectively
  • Good knowledge of memory layout topology; experience with memory compilers is a plus
  • Knowledge of AI, automation in layout, Script Programming, and SKILL Programming
  • Ability to lead new technology reviews and document layout methodologies, flows, and guidelines
  • Self-reliant and able to work independently and collaboratively

Broadcom Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Broadcom and has not been reviewed or approved by Broadcom.

  • Equity Value & Accessibility Equity is used broadly through RSUs with quarterly or annual vesting, and an ESPP with a discount and look‑back that can add meaningful upside. Company disclosures show ongoing equity grants, including inducement RSUs tied to acquisitions, underscoring equity’s central role in total rewards.
  • Retirement Support A 401(k) plan with a competitive company match and immediate vesting is consistently highlighted, supporting long‑term savings. Tax‑advantaged accounts like HSA/FSA further strengthen the financial wellness toolkit.
  • Pay Growth & Progression Compensation ceilings in technical tracks are described as high, with wide ranges and very strong totals for experienced engineers. Sales compensation is also characterized as competitive, supporting attractive on‑target earnings.

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The Company
HQ: Palo Alto, CA
38,985 Employees
Year Founded: 1991

What We Do

Broadcom Inc. (NASDAQ: AVGO) is a global technology leader that designs, develops and supplies semiconductor and infrastructure software solutions.

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