About this opportunity:
Low-power RTL design often leans on established "best practices" - Gray-coded counters, clock-gated FSMs, RAM-based FIFOs, and more. These techniques are widely accepted, yet their true PPA (Power, Performance, Area) impact is rarely quantified in a controlled, isolated way. Assumptions may break under realistic parameterization, specific conditions, or different technology nodes.
In this thesis, you will deliver quantified, evidence-based characterization of common low-power RTL patterns. Instead of rules of thumb, you will systematically sweep design alternatives for the same function, measure them (including glitch power), and identify the knee points where a technique starts to pay off. You will leverage GenAI tooling to accelerate RTL variant and stimuli generation and enable broad design-space exploration. Deliverables include a reusable low-power component library, a proof-of-concept flow, and an HTML "cookbook" dashboard showing savings and trends. Results will reveal relative trends and knee points between design choices - not replace post-layout, sign-off-quality power analysis.
What you will do:
- Characterize common RTL design patterns for power (dynamic, static, glitch), performance, and area in an idealized/controlled scope.
- Build and use an Ericsson-silicon-specific analysis framework based on pre-layout netlist context, gate-level simulation (GLS) for accurate activity annotation, and glitch power analysis to capture secondary glitch contributions often missed by standard methods.
- Confirm or challenge widely held low-power assumptions with hard numbers.
- Identify knee points for savings via parametric modules (e.g., as a function of width, depth, activity).
- Create a reusable low-power RTL component library with documented savings (internal git repo).
- Cover common IP building blocks with multiple functionally equivalent variants, for example:
- Muxes (one-hot, AND-OR with registered selects, avoiding cascaded priority chains)
- Memories (per-bank enable gating, Gray-coded address pointers, validation/quantification of sleep/retention modes, entry/exit energy cost, wake-up latency trade-offs)
- FIFOs (shift-based vs. RAM-based restructuring, per-entry write gating)
- Counters (Gray-coded, LFSR, segmented high-bit counters)
- Control FSMs (clock-gated with registered one-hot selects, Gray state encoding for sequential transitions)
- Interfaces (clock-gated arbiters, balanced grant trees, crossbars)
- Package the findings into a proof-of-concept flow and an HTML dashboard "cookbook" that presents measured savings and trends.
The skills you bring:
- Master's studies in Electrical/Computer Engineering, Computer Science, or similar.
- Background in computer architecture, ASIC design, RTL HDL coding, and testbench design using SystemVerilog.
- Working knowledge of UVM and scripting (Tcl/Python) for EDA tools is preferred.
- Curiosity to validate conventional wisdom with data, and discipline to design controlled experiments.
Why join Ericsson?
At Ericsson, you'll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what's possible. To build solutions never seen before to some of the world's toughest problems. You'll be challenged, but you won't be alone. You'll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.
What happens once you apply?
Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.
Primary country and city: Sweden (SE) || Stockholm
Req ID: 791542
Skills Required
- Master's studies in Electrical Engineering, Computer Engineering, Computer Science, or a similar field
- Background in computer architecture
- Background in ASIC design
- RTL HDL coding experience
- Testbench design using SystemVerilog
- Working knowledge of UVM
- Scripting experience with Tcl or Python for EDA tools
- Ability to design controlled experiments and validate assumptions with data
What the Team is Saying
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Ericsson Compensation & Benefits Highlights
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Healthcare Strength — U.S. job postings describe multiple medical plan options (including PPO and HSA‑eligible HDHP) plus dental and vision, aligning with a comprehensive medical suite. Corporate materials also emphasize wellbeing resources and EAP support.
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Retirement Support — Company communications and U.S. materials reference market‑competitive retirement benefits, including a 401(k) with automatic employer contributions and additional matching. Investor and benefits materials signal a structured approach to total rewards that includes long‑term savings programs.
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Parental & Family Support — U.S. and EWS guides and postings highlight paid maternity and parental/adoption leave at full pay, alongside structured short‑term disability at full pay for defined weeks by tenure. These programs are positioned as part of a family‑friendly, work‑life‑balance offering.
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What We Do
Ericsson builds the digital connectivity the world relies on. Our technology underpins the mobile networks, platforms, and systems that billions of people, businesses, and societies depend on every day. We are a global leader in communications technology, delivering mobile network infrastructure, cloud software, and wireless connectivity solutions for service providers and enterprises worldwide. Our networks support connectivity across 180+ countries, helping power everyday communication as well as critical digital services at global scale. Connectivity has evolved far beyond consumer mobile use. Today, nearly 80% of the world’s population accesses the internet via mobile networks, and Ericsson is helping shape what comes next. We are advancing 5G and 5G Advanced, developing network APIs that open connectivity to the global developer ecosystem, and applying automation and AI to make networks more intelligent, efficient, and resilient. Ericsson was the first company to launch live 5G networks on five continents, and our 5G platform is now commercially live in 150+ networks across 60+ countries. We also support more than 36,000 enterprise customers, enabling secure, high-performance connectivity for industries such as manufacturing, aviation, logistics, utilities, and public safety, where reliability and performance are mission critical. Innovation is central to how we work. Ericsson has approximately 28,000 employees in research and development, backed by one of the strongest intellectual property portfolios in the industry with 60,000+ granted patents. Our engineers, researchers, and technologists work across 100+ global R&D sites, helping define how networks evolve and how digital infrastructure is built for the long term. As the world moves toward a mobile-first, AI-powered, and cloud-driven future, connectivity becomes the foundation for digital transformation across every industry. Ericsson is building that foundation, shaping the future of digital connectivity through technology that operates at global scale and supports real-world impact, today and for what comes next.
Why Work With Us
Ericsson is a place for people who want to work on technology that powers everyday life. You’ll contribute to large-scale systems used every day, tackle complex challenges in live environments, and keep developing your skills and career in your own vision.
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