Master Thesis: Early Prediction and Optimization of power, Perfomance and Area

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About this opportunity
Would you like to help digital design teams understand how an RTL design is likely to perform before completing time-consuming synthesis and physical implementation?
Power, performance and area, commonly referred to as PPA, are critical design objectives in advanced digital systems. However, reliable PPA results are often available only at a relatively late stage of the development process. At that point, addressing an inefficient architectural or RTL design choice may require significant redesign and repeated implementation runs.
Early estimates derived from RTL can differ considerably from final implementation results because they do not fully account for factors such as technology mapping, switching activity, buffering, placement and routing. In this thesis, you will investigate how RTL characteristics, simulation activity data and results from completed implementation runs can be combined to improve early PPA prediction. The goal is not only to produce more accurate estimates, but also to turn the findings into practical, actionable feedback for RTL and IP designers.
What you will do
You will work with one or more representative RTL designs and the associated simulation, synthesis, power and implementation data. You will establish PPA baselines and investigate how different RTL structures, architectural decisions and synthesis configurations affect power consumption, timing performance and silicon area.
You will have the opportunity to help shape the detailed direction of the thesis. Areas of investigation may include:
Correlating characteristics visible at RTL level with PPA results obtained after synthesis or physical implementation
Analysing the PPA impact of common design structures, including:
Multipliers and adders
Filters and multiplexers
Combinational and register-based logic
Pipelines, register placement and clock-gating opportunities
Comparing alternative RTL or architectural implementations that provide equivalent functionality
Evaluating synthesis configurations and optimisation priorities for power, timing and area
Using simulation activity data, such as VCD or FSDB data, to improve power analysis
Exploring data-driven, automated or AI-assisted methods for identifying PPA optimisation opportunities
Developing a reusable methodology or prototype flow that provides actionable feedback to RTL and IP designers
Verifying that proposed optimisations preserve functional correctness and satisfy relevant timing and area requirements
The expected outcome is a systematic and reusable approach for identifying PPA optimisation opportunities earlier in the development process. By moving this analysis closer to the RTL design stage, the work could improve PPA predictability, reduce manual investigation and limit the number of iterations between RTL development, synthesis and physical implementation.
The skills you bring
You are pursuing a Master's degree in Electrical Engineering, Computer Engineering, Computer Science, Embedded Systems or a related field
You have knowledge of digital design and computer architecture
You have a basic understanding of RTL design using Verilog, SystemVerilog or VHDL
You are interested in power, performance and area analysis
You can work methodically with experimental data and evaluate alternative design solutions
You are eager to learn about semiconductor design, synthesis and physical implementation flows
Experience in one or more of the following areas would be an advantage:
Logic synthesis or ASIC design flows
Digital simulation and waveform activity data
Scripting or programming using Python, Tcl or a similar language
Data analysis, machine learning or AI-assisted engineering methods