Lead Verification Engineer

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• MSEE/BSEE with 8+ years in chip validation.

• Experience with PCIe Gen5/6 designs and its Silicon validation is required

• Experience in planning the Si validation process and creating realistic schedule estimates.
• Strong experience in high level Object Oriented with C/C++, System Verilog is must

• Experience with debug of SW drivers, HW designs and FW code is required

• Experience with debug uC based chips and FW is a plus

• Experience in understanding standards like PCI-SIG and its validation, knowledge of PCIE protocol and its physical layer implementations/SERDES is a big plus.

• Deeper understanding of PLLs/CDR concepts/AMS interfaces and networking IP designs are preferred.
• Experience writing tests, scripting languages such as PERL, TCL Unix Scripting and managing regression analysis
• Strong debugging skills of Verilog RTL & test environment is desired
• Able to adopt the use of new techniques and methodologies and promote their use within the project.
• Shall be pro-activity, self-organized, drive solutions and ability to works with teams/leads across time zones

Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.

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