Lead Software Engineer - Low-Power Verification

Posted 8 Hours Ago
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San Jose, CA, USA
In-Office
115K-213K Annually
Mid level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Develop and improve UPF compilation software for Palladium and Protium platforms, focusing on performance, correctness, IEEE 1801 support, low-power verification flows, and documentation. Collaborate with R&D, PE, and AE teams to deploy UPF solutions across emulation and prototyping workflows. Contribute to compiler unification, self-checks, example-driven validation, and support for SystemVerilog, Verilog, and VHDL-based designs.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Join our team and help build the next generation of low-power verification software for the Palladium and Protium emulation and prototyping platforms. 

As a Lead Software Engineer on the Palladium and Protium UPF R&D team you will be responsible for improving UPF compilation performance and correctness, adding support for new IEEE 1801 LRM revisions, and rebuilding UPF documentation around end-to-end workflows for multi-billion-gate low-power designs.

What you will do

  • Contribute to the UPF compilation flow -- improve compilation performance, reduce instrumented capacity, and add self-checks across Parallel Partition Compiler (PPC) and Modular Compiler (MC) flows, including Dielet UPF support.

  • Rebuild UPF documentation around end-to-end compilation workflows, backed by valid SystemVerilog and UPF examples, and keep code and docs in sync through example-driven checks.

  • Work with R&D, PE and AE teams to deploy UPF solutions across key flows (AVIP, UVMA, MC, and Dielets -- each with UPF in 2- and 4-state).

  • Help consolidate and unify UPF compilation across Palladium and Protium.

What we are looking for

  • BS in CS, EE, or a related field with 4+ years of experience; MS with 2+ years; PhD with 1+ year; or equivalent practical experience.
  • Working knowledge of IEEE 1801 UPF and RTL languages (Verilog, SystemVerilog, VHDL).
  • Ability to read, review, and reason about C++ code and object-oriented designs.
  • Scripting experience in Perl, Tcl/Tk, and/or Python.
  • Fluency with AI-assisted coding tools (Copilot, Claude, Cursor, or equivalent), with critical evaluation of AI output.
  • Strong technical writing skills — able to author user guides, specifications, and workflow-first documentation.

The annual salary range for California is $114,800 to $213,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • BS in Computer Science, Electrical Engineering, or a related field with 4+ years of experience
  • MS in Computer Science, Electrical Engineering, or a related field with 2+ years of experience
  • PhD in Computer Science, Electrical Engineering, or a related field with 1+ year of experience
  • Equivalent practical experience
  • Working knowledge of IEEE 1801 UPF
  • Working knowledge of RTL languages including Verilog, SystemVerilog, and VHDL
  • Ability to read, review, and reason about C++ code and object-oriented designs
  • Scripting experience in Perl, Tcl/Tk, and/or Python
  • Fluency with AI-assisted coding tools such as Copilot, Claude, Cursor, or equivalent
  • Strong technical writing skills for user guides, specifications, and workflow-first documentation

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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