High-performance and Power-Critical CPU and/or GPU Implementation and Methodology Engineer
Responsibilities / Skills
· Full-chip and block-level implementation from RTL to Signoff, including place-and-route, timing closure, physical verification, power analysis, and optimization.
- Strong understanding of physical design fundamentals including floorplanning, placement, clock tree synthesis, routing, timing analysis, signal integrity, IR drop, and electromigration.
- Experience with timing closure methodologies for setup, hold, power, and area optimization.
- Familiarity with low-power implementation techniques including UPF/CPF, power gating, multi-voltage designs, clock gating, and leakage optimization.
- Need to be automation savvy and able to develop scripts, utilities, and methodologies to improve productivity and design quality.
- Prior experience in Python, Tcl, Perl, Shell, or other programming/scripting languages is a plus.
- Exposure to machine learning and AI-assisted optimization techniques is a plus.
- Familiarity with industry-standard implementation and signoff tools
- Understanding of advanced technology nodes (5nm and below) and associated challenges including congestion, variability, power integrity, and manufacturability is desirable.
- Strong debugging and problem-solving skills with the ability to analyze complex design issues and drive them to resolution.
- Good communication skills and ability to work effectively with cross-functional teams including architecture, RTL, verification, methodology, and CAD teams.
- Experience with data analytics, design-space exploration, or AI-driven optimization frameworks for improving PPA and productivity is highly desirable.
- Experience in PPA optimization, design convergence, benchmarking, methodology development, and large-scale CPU/GPU implementation is a plus.
The annual salary range for California is $119,000 to $221,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.Skills Required
- Full-chip and block-level implementation from RTL to signoff
- Experience with place-and-route, timing closure, physical verification, power analysis, and optimization
- Strong understanding of floorplanning, placement, clock tree synthesis, routing, timing analysis, signal integrity, IR drop, and electromigration
- Experience with setup, hold, power, and area optimization methodologies
- Familiarity with low-power implementation techniques including UPF/CPF, power gating, multi-voltage designs, clock gating, and leakage optimization
- Automation skills for developing scripts, utilities, and productivity methodologies
- Familiarity with industry-standard implementation and signoff tools
- Strong debugging and problem-solving skills
- Good communication and cross-functional collaboration skills
- Prior experience with Python, Tcl, Perl, Shell, or other scripting languages
- Exposure to machine learning and AI-assisted optimization techniques
- Understanding of advanced technology nodes, including 5nm and below
- Experience with data analytics, design-space exploration, or AI-driven optimization frameworks
- Experience in PPA optimization, design convergence, benchmarking, methodology development, and large-scale CPU/GPU implementation
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
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Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
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Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
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Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
Cadence Design Systems Insights
What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
