Responsibilities :
- Design Verification for interconnect IP and Tensilica Processor subsystems.
- Relevant experience in interconnect and subsystems is strongly preferred
- Crafting verification plans and executing on those plans to verify highly complex and configurable designs.
- Responsible for coverage collection and closure
- Work closely with cross functional teams (DV/Arch/Design/FW) to identify coverage scope
- Responsible for creating / working with UVM based DV environment.
Required Skills and Experience:
- 7+ years of design verification experience
- BS (or higher) in EE/Computer Engineering
- Strong technical and interpersonal skills
- Excellent knowledge of Interconnects, NoCs and design verification fundamentals.
- Excellent knowledge and command over AMBA protocols like AXI, AHB and APB.
- Thorough understanding of System Verilog, UVM, and other programming languages to build flexible and reusable complex testbenches
- Exposure to scripting languages like Perl, Unix shell or similar languages
- Understanding of Coherency concepts will be a plus
- Experience with Formal Verification will be a plus
- Experience with development of fully automated flows
- Experience with Gate Level Simulations
- Excellent written and oral communication skills necessary
- Experience with integrated verification flows for processors with C and SV language is a plus
- Good experience with Simulation and Debugging tools like Cadence Xcelium, Indago etc.
Skills Required
- 7+ years of design verification experience
- BS (or higher) in EE/Computer Engineering
- Strong technical and interpersonal skills
- Excellent knowledge of Interconnects, NoCs and design verification fundamentals
- Excellent knowledge and command over AMBA protocols like AXI, AHB and APB
- Thorough understanding of System Verilog, UVM, and other programming languages to build flexible and reusable complex testbenches
- Exposure to scripting languages like Perl, Unix shell or similar languages
- Experience with development of fully automated flows
- Experience with Gate Level Simulations
- Excellent written and oral communication skills
- Good experience with Simulation and Debugging tools like Cadence Xcelium, Indago
- Relevant experience in interconnect and subsystems
- Understanding of Coherency concepts
- Experience with Formal Verification
- Experience with integrated verification flows for processors with C and SV language
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
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Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
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Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
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Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
Cadence Design Systems Insights
What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.








