- Be a Pioneer: Get in on the ground floor of a hypergrowth startup! You’ll be part of a small, dynamic team where your contributions are visible from day one.
- Accelerated Growth: Work directly alongside industry veterans. This is a fast-track environment designed to turn a junior engineer into an expert.
- Make an Impact: Your work ensures the quality and reliability of disruptive technology.
- Rewarding Compensation: We offer a competitive salary, bonus potential, and meaningful equity.
- Flexibility: Benefit from a hybrid work model and flexible time off.
- RTL Integration: Assist in integrating DFT features such as scan compression, memory BIST, IEEE 1149, IEEE 1687, and IEEE 1500 wrappers into the design.
- Scan & ATPG: Execute scan insertion scripts and run ATPG (Automatic Test Pattern Generation) for various fault models, including stuck-at and transition faults.
- Simulation & Debug: Run and debug gate-level simulations (GLS) to verify DFT structures and investigate simulation mismatches.
- Coverage Analysis: Help identify areas of low test coverage and work with senior engineers to implement logic changes or test points to improve results.
- Verification: Support the validation of test patterns for low-power designs and assist in timing constraint verification for scan modes.
- Automation: Maintain and improve Tcl, Perl, or Python scripts to streamline the DFT flow and post-processing of design data.
- Experience: 1–3 years of experience in DFT or Digital Design (relevant internships or university projects count!).
- Education: A Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Core Knowledge: A strong understanding of digital logic design, Verilog/SystemVerilog, and basic DFT concepts (Scan, ATPG, BIST).
- Scripting Skills: Familiarity with Tcl, Python, or Perl for workflow automation.
- Tool Exposure: Basic experience or academic exposure to industry-standard tools (e.g., Cadence Modus/Genus, Synopsys Tessent/DFTMAX, or Siemens Fastscan).
- Mindset: A "can-do" attitude, a desire to learn complex hierarchies, and excellent communication skills for cross-functional collaboration.
- Knowledge of RISC-V architecture or CPU fundamentals.
- Experience with Gate Level Simulations (GLS) and timing analysis.
- Exposure to hardware description languages like VHDL or specialized DFT protocols like IJTAG (IEEE 1687).
- Knowledge or experience using ATE test systems (Advantest 93K, Teradyne Ultra-Flex, etc).
What We Do
InspireSemi provides revolutionary high-performance, energy-efficient accelerated computing solutions for High-Performance Computing (HPC), AI, graph analytics, and other compute-intensive workloads. The Thunderbird “supercomputer-cluster-on-a-chip” is a disruptive, next-generation datacenter accelerator designed to address multiple underserved and diversified industries, including financial services, computer-aided engineering, energy, climate modeling, cybersecurity, and life sciences & drug discovery. Based on the open standard RISC-V instruction set architecture, InspireSemi’s solutions set new standards of performance, energy efficiency, and ease of programming. The Company is headquartered in Austin, TX and led by an accomplished team with a proven track record. It is leveraging an efficient, scalable fabless operating model with outsourced manufacturing partners (e.g.- TSMC, ASE). Leading industrial companies, national labs, and computer OEMs value our technology, innovative North America design team, and world-class supply chain partners.
