IP Logic Design Engineer

Job Details:

Job Description: The Role and Impact: As an IP Logic Design Engineer, you will play a pivotal role in driving Intel's innovation by developing cutting-edge logic designs for high-performance IPs integrated into SoC products. Your contributions will directly impact Intel's ability to deliver world-class products across Client, Graphics, and Data Center markets. In this role, you will collaborate with cross-functional teams to define architectures, optimize logic, and ensure the seamless integration of IPs into the broader chip design. This position offers a unique opportunity to shape the future of digital design while leveraging your technical expertise to deliver reliable, power-efficient, and high-quality IP solutions. Key Responsibilities: - Own and deliver logic design and RTL implementation for IP development, ensuring sign-off verification for functionality, reliability, and synthesis checks. - Develop architecture and microarchitecture specifications for logic components, driving area, power, and performance optimizations. - Apply advanced strategies and tools for RTL coding, simulation, and debug, ensuring designs meet power-performance-area (PPA) goals and timing integrity. - Collaborate with verification teams to review and execute verification plans, resolve failing RTL tests, and implement corrective measures to ensure design feature correctness. - Support SoC integration efforts, ensuring high-quality IP handoffs and seamless integration into full-chip designs. - Drive post-silicon validation, debug, and high-volume manufacturing support for IPs. - Manage stakeholder relationships across logic verification, digital backend, and SoC teams, ensuring alignment on implementation and design objectives.

Qualifications:Minimum Qualifications: - Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with 6+ years of experience in logic design and RTL development. - Expertise in System Verilog and RTL coding, including advanced digital design techniques. - Demonstrated experience in clock domain crossing, debugging microarchitecture/simulation, and static timing analysis. - Proficiency in low-power design strategies, including clock gating and UPF methodologies. - Familiarity with tools and techniques such as LINT, CDC, RDC, timing/synthesis, and regression/code coverage. - Strong analytical skills and hands-on experience resolving pre-silicon and post-silicon design challenges. Preferred Qualifications: - Master's degree in Electrical Engineering, Computer Engineering, or a related field, with 5+ years of relevant experience. - Knowledge of AMBA protocols (CHI, AXI, AHB, APB), PCIe, and CXL standards. - Background in architecture and microarchitecture development for IP subsystems. - Experience working with physical design teams to address timing and backend implementation issues. - Familiarity with mixed-signal designs, behavioral coding, and simulations. - Understanding of PPA trade-offs and innovative design solutions. - Excellent communication skills and a proven ability to collaborate across geographically distributed teams. Join Intel's mission to create innovative technologies that enrich and empower our global community. Apply today to be part of a team that drives digital evolution and shapes tomorrow's innovations.

          

Job Type:Experienced Hire

Shift:Shift 1 (India)

Primary Location: India, Bangalore

Additional Locations:

Business group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.