HBM SoC Design Engineer

Our vision is to transform how the world uses information to enrich life for all .
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the steadfast pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing.
As a SoC Design Engineer, you will be part of the Heterogeneous Integration Group (HIG), contributing to the design, development, and integration of next-generation HBM SoC logic die. You will work closely with architecture, verification, physical design, firmware, and product teams to implement robust, high-performance SoC solutions that meet ambitious power, performance, area, and schedule targets.
This is a hands-on technical role focused on RTL design, IP integration, debugging, and pre/post-silicon support.
Key Responsibilities

• Design and implement RTL for SoC-level blocks and subsystems used in HBM logic die.
• Integrate internal and third-party IP (e.g., controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY-adjacent logic).
• Collaborate with SoC architects to translate architectural and micro-architectural specifications into high-quality RTL implementations.
• Participate in SoC-level integration activities, including clocking, reset, power intent, and configuration infrastructure.
• Support design verification through debug of simulation, emulation, and formal results; resolve functional, performance, and connectivity issues.
• Work closely with physical design teams to address synthesis, timing, power, and floor planning considerations.
• Assist with pre-silicon validation and post-silicon bring-up, including root-cause analysis of silicon issues.
• Contribute to design documentation, block specifications, and design reviews.
• Collaborate multi-functionally with Product Engineering, Test, Probe, Process Integration, and Manufacturing to ensure robust and manufacturable builds.
• Continuously improve build quality, reusability, and development efficiency through established guidelines and automation.

Qualifications

• Strong experience in digital SoC design and RTL development.
• Proficiency in SystemVerilog/Verilog and familiarity with SoC integration methodologies.
• Experience with the RTL-to-GDS flow, including synthesis, static timing analysis, and design sign-off considerations.
• Working knowledge of design verification concepts and debug workflows.
• Experience integrating complex IP blocks into large SoCs.
• Familiarity with EDA tools from Cadence, Synopsys, and/or Siemens.
• Programming or scripting experience (e.g., Python, TCL, Perl, or shell scripting).
• Ability to work effectively in a global, multi-functional engineering environment.
• Strong analytical and problem-solving skills with attention to detail.

Preferred Qualifications

• Experience with HBM, DRAM, or memory-centric SoC designs.
• Familiarity with high-speed interfaces, clocking strategies, reset architectures, and power management concepts.
• Exposure to DFT concepts (scan, MBIST, BIRA/BISR) and debug.
• Experience with hardware emulation or acceleration platforms (e.g., Palladium, Veloce, Zebu).
• Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field.
• Minimum 10 years of experience in a related field.
• Proven ability to mentor and develop engineers early in their careers.
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum 10 years of experience in a related field.
• Proven ability to mentor and develop engineers at early career stages.

The US base salary range that Micron Technology estimates it could pay for this full-time position is:
$162,000.00 - $344,000.00 a year
Additional compensation may include benefits, bonuses and equity.
Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits .
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
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