FPGA IP Software Development Engineer

Posted 7 Days Ago
Be an Early Applicant
Penang, Daerah Timor Laut, Penang, MYS
In-Office
Entry level
Artificial Intelligence • Internet of Things • Machine Learning
The Role
Design and simulate RTL for FPGA IP and subsystems, participate in FPGA development flow, perform logic coding and simulation, debug and analyze design issues, and collaborate with verification and backend teams.
Summary Generated by Built In
Job Details:

Job Description:

Join the exciting new journey of Altera as we march towards a stand-alone company. From the IoT to the data center, Altera offers a broad portfolio of programmable logic solutions that allow customers to solve a wide variety of system level challenges.

  • Be part of a talented wireless design team

  • Be at the forefront of innovation by working on leading edge technology to design blazing next generation wireless IP.

Responsibility includes:

  • Performs logic design RTL coding and simulation to develop IPs and subsystems designs

  • Understanding of processes in the FPGA development flow

  • Analysis of problem at hand and presenting of solutions.

Qualifications:

Education

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

  • Coursework or projects in VLSI, Digital Design, and Computer Architecture.

Technical Skills

RTL Design & Hardware Description Languages

  • Basic experience with Verilog or VHDL for digital design.

  • Understanding of combinational & sequential logic, finite state machines (FSMs), and pipeline architectures.

Simulation & Verification Basics

  • Exposure to testbenches, functional simulation using ModelSim, VCS, or Xcelium.

  • Basic understanding of SystemVerilog assertions (SVA) and testbenches.

  • Awareness of UVM (Universal Verification Methodology) is a plus.

Synthesis & Timing Analysis (Preferred)

  • Basic knowledge of synthesis flow (Design Compiler, Genus, or Vivado).

  • Understanding of setup/hold timing violations and static timing analysis (STA).

Scripting & Automation

    • Basic understanding of AMBA protocols (AXI, AHB, APB).

    • Awareness of memory subsystems, clock domains, and reset strategies.

    • Exposure to industry standards like PCIe, USB, DDR, or MIPI is a plus.

    Experience & Projects

    • Internships or academic projects related to RTL design, FPGA prototyping, or digital system design.

    • Hands-on experience in FPGA-based projects using Xilinx or Intel FPGA tools is an advantage.

    Soft Skills

    • Problem-solving: Ability to debug design issues.

    • Communication: Ability to document designs and discuss technical topics clearly.

    • Collaboration: Willingness to work with verification and backend teams.

    Job Type: Regular

    Shift:Shift 1 (Malaysia)

    Primary Location:Penang 15, Penang, Malaysia

    Additional Locations:

    Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

    Skills Required

    • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
    • Coursework or projects in VLSI, Digital Design, and Computer Architecture
    • Basic experience with Verilog or VHDL for digital design
    • Understanding of combinational and sequential logic, FSMs, and pipeline architectures
    • Exposure to testbenches and functional simulation using ModelSim, VCS, or Xcelium
    • Basic understanding of SystemVerilog assertions (SVA) and testbenches
    • Awareness of UVM (Universal Verification Methodology)
    • Basic knowledge of synthesis flow (Design Compiler, Genus, or Vivado)
    • Understanding of setup/hold timing violations and static timing analysis (STA)
    • Basic understanding of AMBA protocols (AXI, AHB, APB)
    • Awareness of memory subsystems, clock domains, and reset strategies
    • Exposure to industry standards like PCIe, USB, DDR, or MIPI
    • Internships or academic projects related to RTL design, FPGA prototyping, or digital system design
    • Hands-on experience in FPGA-based projects using Xilinx or Intel FPGA tools
    • Problem-solving, documentation, communication, and collaboration skills

    Altera (altera.com) Compensation & Benefits Highlights

    The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Altera (altera.com) and has not been reviewed or approved by Altera (altera.com).

    • Retirement Support Feedback suggests retirement programs are robust, with offerings such as a 401(k) and a pension. This breadth supports long-term financial security.
    • Leave & Time Off Breadth Feedback suggests time-off policies are generous, including PTO, paid sick days, and paid holidays. Wellness initiatives like gym memberships further support balance.
    • Parental & Family Support Feedback suggests parental leave is generous. Family-building support, including fertility benefits and adoption reimbursement, is highlighted as part of the package.

    Altera (altera.com) Insights

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    The Company
    HQ: San Jose, California
    1,612 Employees
    Year Founded: 1983

    What We Do

    Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.

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