Key responsibilities:
- Define FPGA architecture for:
- Real‑time communication and control loops.
- Power electronics–specific functions (PWM, gating, protection, measurements).
- Partition functions between FPGA, MCU/DSP, and other devices considering latency and determinism.
- Select appropriate FPGA families and IP for timing‑critical and safety‑related functions.
- Develop synthesizable RTL (VHDL) for:
- PWM generators (e.g., carrier‑based, space‑vector, multi‑phase, interleaved, dead‑time insertion, synchronised to grid or rotating frame).
- Real‑time communication interfaces (e.g., synchronous serial links, fieldbus/industrial Ethernet PHY interfaces, deterministic point‑to‑point links, custom high‑speed serial).
- Signal and clock reconstruction blocks (e.g., digital PLLs, phase tracking, clock domain crossing, resampling, and timestamping).
- Measurement, protection, and monitoring logic (e.g., overcurrent, overvoltage, desaturation, fault latching, fast trips).
- Implement:
- High‑resolution timers and counters for gating signals.
- Clock, reset, and synchronization schemes for multi‑board/multi‑FPGA systems.
- Fixed‑point digital signal processing as needed for filtering, estimation, or modulation.
- Develop testbenches and simulations to verify:
- PWM timing accuracy, dead‑time behavior, and jitter performance.
- Real‑time communications latency, robustness, and error handling.
- Correct operation of signal/clock reconstruction (phase tracking, frequency changes, grid disturbances).
- Perform static timing analysis and timing closure for:
- Tight real‑time constraints (fast control loops, sub‑µs reaction times).
- Multiple clock domains and asynchronous interfaces.
- Support lab and field testing:
- Board bring‑up and system integration.
- Debugging under real operating conditions using oscilloscopes, logic analyzers, current/voltage probes, and protocol analyzers.
- Create and maintain documentation:
- FPGA specifications, timing budgets, and interface definitions.
- Verification plans, test reports, and release notes.
- Support production and field updates (JTAG, in‑system programming, secure and fail‑safe update mechanisms).
Your Profile:
- Bachelor’s or Master’s degree in Electrical Engineering, Information Technology, Computer Engineering, or a related field, with a focus on FPGA or digital hardware design.
- Several years of professional experience in FPGA design, preferably in real-time, control, or power electronics applications.
- Strong proficiency in VHDL and a solid understanding of synthesizable RTL design, timing constraints, and clock domain crossing techniques.
- Hands-on experience with at least one major FPGA vendor toolchain.
- Experience with time-critical logic such as PWM generation, high-resolution timers, or communication interfaces.
- Fluency in English is required; German is a plus.
Key Competencies:
- Strong problem‑ solving skills in time‑critical and safety‑related systems.
- High attention to detail, especially regarding timing, jitter, and protection logic.
- Ability to collaborate with control, power electronics, hardware, and firmware teams.
- Clear communication of complex timing and architecture decisions.
We offer:
Company bound by a collective bargaining agreement with 35 hours/week and 30 days of vacation
Flexible working time arrangements
On-site canteen in Berlin
Welcome Days for the perfect start in a global company
Relocation Assistance Provided: No
Skills Required
- Bachelor's or Master's degree in Electrical Engineering or related field
- Several years of professional experience in FPGA design
- Strong proficiency in VHDL
- Hands-on experience with FPGA vendor toolchain
- Experience with PWM generation and high-resolution timers
GE Vernova Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about GE Vernova and has not been reviewed or approved by GE Vernova.
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Retirement Support — The 401(k) plan includes company matching contributions and additional company retirement contributions, with access to Fidelity resources and financial planning consultants. Feedback suggests this structure supports long-term savings beyond a basic match.
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Parental & Family Support — Paid parental leave is available with flexible, continuous or non-continuous usage, and is complemented by adoption resources and Work/Life Connections guidance. Maternity leave is described as extended relative to typical workplace norms.
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Leave & Time Off Breadth — Time-off programs include 12 paid holidays, permissive time off for many salaried roles, and dedicated personal, illness, and caregiving time for U.S. new hires. Some hourly roles start with a defined PTO bank, while other roles may offer unlimited time off.
GE Vernova Insights
What We Do
GE Vernova is a planned purpose-built company on a mission to electrify the planet while simultaneously working to decarbonize it. If we want our energy future to be different…we must be different. Our mission is embedded in our name. We retain our treasured legacy, “GE,” in our name as an enduring and hard-earned badge of quality and ingenuity. “Ver” / “verde” signal Earth’s verdant and lush ecosystems. “Nova,” from the Latin “novus,” nods to a new, innovative era of lower carbon energy that GE Vernova will help deliver. GE Vernova brings together GE’s portfolio of energy businesses including Power, Wind, Electrification and Digital businesses. With focus, GE Vernova is accelerating the path to more reliable, affordable, and sustainable energy, while helping our customers power economies and deliver the electricity that is vital to health, safety, security, and improved quality of life. Together, we have The Energy to Change the World.
Why Work With Us
Join our team, to evolve and grow, surrounded by some of the brightest minds in the industry who help you get better every day. You’ll get the chance to rewrite the rules, work on cutting-edge technology, and be part of a global team for positive change.
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