The demand for new data centers and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck means rethinking the fundamental architecture of inference compute. The industry's current path can't meet the need, so we're taking a different approach.
Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.
We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others.
Join us and shape the future of computing!
Position OverviewWe are seeking a talented Firmware Engineer to join our engineering team. This role is focused on low-level firmware development for our novel LLM accelerator architecture. You will develop code for the firmware layer that directly controls our custom hybrid optical-electronic compute hardware, ensuring reliable operation and optimal performance.
LocationAustin, TX
Key ResponsibilitiesFirmware Development:
Contributing to low-level firmware to orchestrate execution of LLM workloads across hardware accelerator components
Contributing to system and board management of such a system
Create debugging and profiling tools for firmware and hardware interaction
System Integration:
Collaborate with hardware engineers to define software-hardware interfaces
Optimize end-to-end performance from application layer to hardware execution
Develop comprehensive testing and validation frameworks
Create documentation and specifications for firmware interfaces
Support customer integration and provide technical guidance
Education: Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or related field
Experience: 3–5 years of professional experience in firmware engineering, embedded systems, or low-level systems programming
Programming: High proficiency in embedded C++ (essential), Python for tooling and automation
Embedded Systems: Experience with embedded systems programming and hardware interfaces
Systems Knowledge: Familiarity with computer architecture, memory hierarchies, and parallel computing concepts
Hardware Interfaces: Experience with hardware communication protocols and register-level programming
Education: Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or related field
Bus Protocols: Experience with lower speed peripheral busses (I2C/SPI/UART/CAN/LIN), Some experience with PCIe interfaces. Some experience with Ethernet interfaces.
Embedded Processors: Experience with embedded processor architectures (ARM, RISC-V, or similar) and associated toolchains (strongly preferred)
Virtual Platforms: Experience with early firmware development on virtual platforms and/or fast C simulators (preferred)
Cross-Compilation: Hands-on experience with cross-compiler toolchains (preferred)
Containerization: Experience with Docker containers for development and delivery (preferred)
Parallel Debugging: Experience debugging parallel and asynchronous programs (strongly preferred)
Real-Time Systems: Experience with bare metal programming and RTOS (FreeRTOS, Zephyr, or similar) (preferred)
AI-Assisted Development: Experience with structured, human-supervised AI/agentic coding workflows (preferred)
Multi-Node Systems: Experience with multi-node embedded systems, including inter-node communication and coordination (strongly preferred)
Multi-Processor Systems: Experience with multi-processor systems, including IPC and shared memory coordination (preferred)
Adaptive Firmware: Experience designing adaptive and retargetable firmware architectures (preferred)
OTA Updates: Experience with over-the-air update systems for embedded devices (preferred)
RTL Familiarity: Ability to read and understand RTL code for debugging and hardware-software co-design
ML Hardware: Experience with AI/ML accelerators (GPUs, TPUs, FPGAs) and their programming models
Performance Optimization: Experience with high-performance computing and low-latency system design
Thermal/Power Management: Experience with thermal management and power optimization in embedded systems
LLM Knowledge: Familiarity with Large Language Model architectures and their computational requirements (preferred)
High Speed Protocols: Some familiarity or understand of AMBA, AXI, PCIe, on processors and ROCv1/2, Infiniband over networks
Programming Languages: Embedded C++ (essential), Python, Assembly
Bus Protocols: I2C, SPI, UART, or low-speed serial protocols. Ethernet familiarity.
Embedded Processors: ARM Cortex-M/A, RISC-V, or similar; associated toolchains and debugging
Embedded Platforms: Bare metal programming, FreeRTOS, Zephyr, or similar RTOS
RTL & Verification: Verilog/SystemVerilog (reading comprehension), ModelSim, Questasim, or similar simulation tools (nice to have)
Hardware Interfaces: Register-level programming, memory-mapped I/O.
Driver Methodologies: Polling, Interrupt and DMA based hardware interactions
Distributed Embedded: Inter-node communication, message passing, distributed state management (nice to have)
Testing & QA: Unit testing frameworks, hardware-in-the-loop testing, integration testing
CI/CD: Jenkins, GitHub Actions, GitLab CI, or similar systems
Development Tools: CMake, Git, Docker
Debugging Tools: GDB, JTAG debuggers, logic analyzers, oscilloscopes, hardware protocol analyzers
Operating Systems: Posix/Linux (user-space tooling), embedded RTOS internals
Languages: Embedded C++ (primary), Python for tooling, Assembly for low-level optimization
Hardware Tools: JTAG debuggers, logic analyzers, oscilloscopes, protocol analyzers
Simulation: Simulators/Emulators for hardware-software co-verification
Testing: Hardware-in-the-loop testing, automated regression suites, CI pipelines
Focus Areas: Firmware development, HAL implementation, hardware-software co-design
This is an opportunity to play a pivotal role in an innovative startup redefining the future of AI hardware. Work on game-changing technology at the intersection of photonics and AI as part of a collaborative, brilliant team. You’ll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence. Come help us bring this transformative technology to the world.
Join a team that invests in your future and your well-being. At Neurophos, we offer:
100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.
Unlimited PTO. No rigid vacation banks, just a focus on delivery.
401(k) matching and stock option opportunities to ensure our success is your success.
Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.
Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don’t.
Skills Required
- Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or related field
- 3-5 years professional experience in firmware engineering, embedded systems, or low-level systems programming
- High proficiency in embedded C++
- Python for tooling and automation
- Embedded systems programming and hardware interfaces
- Familiarity with computer architecture, memory hierarchies, and parallel computing concepts
- Experience with hardware communication protocols and register-level programming
- Experience with low-speed peripheral buses (I2C, SPI, UART, CAN, LIN)
- Some experience with PCIe interfaces
- Experience with embedded processor architectures (ARM, RISC-V) and toolchains
- Experience with virtual platforms or fast C simulators for early firmware development
- Cross-compilation toolchain experience
- Docker for development and delivery
- Experience debugging parallel and asynchronous programs
- Bare metal programming and RTOS experience (FreeRTOS, Zephyr, or similar)
- Experience with multi-node and multi-processor embedded systems (IPC, shared memory, inter-node communication)
- Ability to read and understand RTL (Verilog/SystemVerilog) for HW/SW co-design
- Experience with AI/ML accelerators (GPUs, TPUs, FPGAs) and programming models
- High-performance computing and low-latency system optimization experience
- Familiarity with CI/CD and testing: Jenkins, GitHub Actions, GitLab CI, unit testing, HIL
- Experience with debugging tools: GDB, JTAG debuggers, logic analyzers, oscilloscopes, protocol analyzers
- Experience with over-the-air update systems for embedded devices
- Familiarity with thermal and power management in embedded systems
- Familiarity with AMBA/AXI, Infiniband, ROCv1/2 or other high-speed protocols
Neurophos Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Neurophos and has not been reviewed or approved by Neurophos.
-
Healthcare Strength — Job postings indicate the company covers 100% of base health plan premiums for employees and dependents and contributes to HSAs. Listings also reference dental, vision, and other voluntary coverages.
-
Leave & Time Off Breadth — Unlimited PTO is advertised with an emphasis on delivery rather than accruals. Notes in postings suggest clarifying typical usage and any minimums.
-
Retirement Support — A 401(k) with employer matching is listed alongside stock option opportunities. This pairing signals structured retirement support in addition to equity participation.
Neurophos Insights
What We Do
Neurophos is an Austin-based semiconductor company developing high-performance, energy-efficient photonic AI inference chips. Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density for an optical system. As AI adoption accelerates, data centers face significant power and scalability challenges. Traditional solutions are struggling to keep up, leading to rapidly rising energy consumption and costs. We’re solving both problems with an OPU that integrates over one million micron-scale optical processing components on a single chip. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving large-scale AI inference performance. We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others. We have also been recognized on the EE Times Silicon 100 list for several consecutive years. Join us and shape the future of optical computing!
Why Work With Us
This is an opportunity to work on a game-changing technology at the intersection of photonics and AI. You’ll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence.
