Jobs at Neurophos

Lead the end-to-end electronic IC program from architecture and specification through ASIC design, verification, tapeout, post-silicon bring-up, and production readiness. Coordinate internal engineering teams and external foundry, IP, OSAT, and design-service partners. Own schedules, dependencies, risks, readiness reviews, tapeout logistics, lab bring-up, silicon debug, and executive reporting. Establish AI-augmented program processes and drive cross-functional execution for a first-silicon mixed-signal ASIC supporting optical AI compute.

Model the architecture and performance of an optical AI inference accelerator through hardware/software co-design. Responsibilities include bringing up transformer and other AI workloads, integrating Hugging Face and PyTorch models, developing Python and C++ functional, performance, energy, and power models, conducting roofline and limiter analyses, modeling memory and compute blocks, simulating RTL, and maintaining reproducible tests, configurations, plots, and reports.

Build functional, performance, energy, power, and area models for AI accelerator workloads and hardware/software co-design. Bring up PyTorch and Hugging Face workloads, model optical GEMM, memory systems, tiling, scheduling, ISA, NoC traffic, and multi-chip mapping. Develop Python analytical models and bit-accurate C++ simulations, contribute to event-driven simulation infrastructure, correlate models with RTL through Verilator and SystemVerilog, establish modeling methodology, and mentor engineers.

Own performance and energy benchmarking for an optical AI inference accelerator. Build reproducible benchmarks across analytical models, architecture models, RTL simulation, and competitor GPUs. Bring up workloads from Hugging Face, PyTorch, papers, and inference stacks; measure latency, throughput, power, and energy; analyze bottlenecks; operate cloud or lab environments; and document configurations, logs, assumptions, and discrepancies.

Lead integration of full-chip or major SoC subsystems, owning top-level flows and cross-domain decisions across DFT, power, timing, and interconnect architecture. Partner with architecture, RTL, physical design, verification, and DFT teams to resolve system tradeoffs. Support organizational growth through hiring and mentoring while remaining hands-on with advanced-node, high-bandwidth, low-power chip designs.

Lead end-to-end physical design and SoC implementation from synthesis through tapeout on advanced process nodes. Build and automate synthesis, timing closure, power, clock, physical verification, and IP/library management flows. Integrate analog and mixed-signal components, support new process technologies, and collaborate with RTL, DV, and analog teams. Build, hire, and manage a multi-site physical design organization delivering optimized GDSII implementations for complex SoCs.

Lead development of a compiler toolchain for a custom LLM accelerator: design IR/graph transformations and lowering passes, optimize compute and memory patterns, integrate with PyTorch/JAX/Triton, build test infrastructure, and ensure correctness and performance for hybrid optical-electronic hardware.

The Principal Analog Design Engineer will design high-speed analog circuits and collaborate with teams to optimize performance in photonic AI systems.

Develop hardware-aware post-training quantization and model adaptation methods for LLMs, diffusion models, and other machine learning applications targeting optical inference hardware. The role involves numerical and constrained optimization, controlled experiments, research-quality implementations, model deployment across PyTorch, Triton, and JAX, GEMM optimization, and collaboration with hardware and software teams to co-optimize AI architectures. The engineer will also publish research while protecting company intellectual property.

Lead Security Engineer to design and defend cloud, network, and systems infrastructure. Implement zero-trust, IAM/PAM, SIEM/EDR, vulnerability management, incident response, vendor/customer security assessments, and drive SOC 2 Type II compliance while partnering with engineering and legal.

Develop low-level firmware for a hybrid optical-electronic LLM accelerator: implement board/system management, hardware interfaces, debugging/profiling tools, validate performance, collaborate on software-hardware integration, and support customer integration.

Lead BEOL process integration for an advanced photonic chip at the foundry in Leuven. Own BEOL process flows, SPC/specification management, DOE and process transfers, fault isolation and failure analysis (SEM/FIB/TEM/EDX), and drive yield, reliability, and continuous improvement while coordinating closely with foundry and internal design teams.

Lead end-to-end datacenter scale-out networking architecture for the T100 platform: host networking stack to EIC PCIe bridge, NIC integration, and DMA into HBM. Define RDMA/transport/offload (RoCEv2, UET), PCIe P2P/ACS policies, queue/completion semantics, vendor selection, collective communication modeling, DPU roadmap, standards representation, and mentor architecture and software engineers.

Lead and build Neurophos' in-house IT function across Sunnyvale and Austin. Own on-prem Linux compute for EDA/CAD, storage, backup, SSO/IdP (Okta), GitHub Enterprise, cloud (Azure) administration, network design, MSP governance, endpoint fleet management, and insourcing roadmap. Design hybrid connectivity, security/compliance evidence, and scale infrastructure from ~50 to 150+ employees while hiring and mentoring the IT team.

Lead development of inference servers and racks, owning electrical, mechanical, and systems engineering from boards and interconnects through rack-level power and high-speed channel closure. Build and lead the Systems team, drive integration/bring-up, EVT/DVT/PVT sign-off, system reliability (RAS), and manage schedule and budget for full-scale product delivery.

Lead software program execution to keep software delivery ahead of hardware by operating hybrid scrum-fall processes, running agile ceremonies, producing forward-looking forecasts with confidence levels, surfacing and driving technical and schedule risks to closure, and coordinating cross-functional dependencies across software, hardware, and cloud while advising chief engineers and executives on scope and sequencing.