Jobs at Neurophos

Design precision optomechanical hardware for free-space optical assemblies, including mounts, fixtures, and alignment stations. Lead tolerance analysis, materials selection, thermal and structural analysis, CAD and GD&T documentation, metrology development, active-alignment integration, prototyping, and manufacturing transfer. Collaborate across optics, photonics, packaging, electrical, and manufacturing teams while mentoring engineers and technicians.

Define and build the company’s optical metrology capabilities across R&D, prototyping, and production. Design and validate custom optical test stations, establish uncertainty budgets and calibration methods, develop measurement data pipelines, and define supplier and incoming-inspection criteria. Support active alignment, production yield analysis, and failure investigation while serving as the technical authority for optical measurement. Lead supplier coordination and eventually hire and mentor metrology engineers and technicians.

Own active-alignment strategy and processes for optical processing unit assemblies, including alignment algorithms, bonding, equipment, automation, station qualification, supplier transfer, production ramp, yield improvement, and reliability testing. Develop alignment-control software and serve as the technical authority for sub-micron and micro-radian optical assembly alignment. Mentor engineers and technicians while collaborating across optical design, optomechanical, metrology, and manufacturing teams.

Leads test strategy and automation for wafer, component, and system-level optical processing units. Builds probe programs, system tests, instrument control, test data infrastructure, traceability, and evidence-based screening criteria. Connects test results across development levels, applies AI/ML to predict downstream behavior, and collaborates on calibration and optical metrology. Hires and manages the test team while remaining hands-on, taking processes from first article through production.

Leads high-speed silicon photonics modulator development from concept through tapeout, fabrication, and testing. Responsibilities include optical, electrical, and RF co-simulation; photonic layout and DRC/LVS sign-off; RF and driver-interface definition; wafer- and die-level characterization; model correlation; and research into advanced modulator architectures. The role also produces design specifications, tapeout reviews, test reports, and technical recommendations while collaborating with IC, packaging, and test teams.

Develops and owns nanofabrication processes for prototype metasurface chips, including multilayer lithography, deposition, etching, planarization, active-layer integration, packaging, and metrology. Characterizes optical and electro-optic device performance, analyzes process data, manages university cleanroom runs, documents recipes and travelers, and feeds as-built measurements into design and modeling. The role also supports mask layout, process transfer to foundries, yield improvement, and mentoring of cleanroom personnel.

Own the end-to-end performance architecture and quantitative modeling of Neurophos’s optical vector-matrix multiplication signal path. Build link and power budgets, model optical, analog, digital, quantization, and algorithmic impairments, allocate accuracy and performance targets, and run Monte Carlo and time-domain simulations. Correlate models with laboratory and silicon measurements, conduct throughput and efficiency trade studies, collaborate across photonic, analog, digital, and software teams, and mentor engineers.

Lead BEOL process integration for an advanced photonic chip at the foundry in Leuven. Own BEOL process flows, SPC/specification management, DOE and process transfers, fault isolation and failure analysis (SEM/FIB/TEM/EDX), and drive yield, reliability, and continuous improvement while coordinating closely with foundry and internal design teams.

Leads end-to-end architecture, performance budgeting, interface control, supplier oversight, hardware and software alignment, laboratory integration, and bring-up of a multidisciplinary photonic computing prototype. Owns the prototype as a long-term experimental platform, designing impairment characterization campaigns, evaluating encoding schemes, maintaining calibration and measurement infrastructure, and translating results into future system architecture decisions.

Leads the analog, mixed-signal, RF, and mmWave IC design organization, from architecture and circuit design through tape-out, validation, qualification, yield ramp, and high-volume production. Builds and mentors the team, defines IP specifications, partners across photonics and systems engineering, drives design-for-manufacturability and test, and owns silicon performance, power, schedule, reliability, and production robustness.

Own the design-for-test architecture and strategy for complex ASICs, including ATPG scan, MBIST, boundary scan, JTAG, HBM, analog test, and wafer/package-level testing. Lead coverage assessment, signoff, test vector development, RTL and physical-design testability, production test-plan delivery, and post-silicon handoff. Establish the company’s DFT flow, metrics, and processes while collaborating with analog, operations, package, physical-design, and OSAT teams.

Own the end-to-end performance model for an optical vector-matrix multiplication engine. Build optical and electrical link budgets, behavioral signal-chain models, and accuracy, throughput, latency, and power allocations. Model noise, distortion, jitter, quantization, crosstalk, mismatch, and nonlinearities using Monte Carlo, corner, and time-domain simulations. Correlate models with laboratory and silicon measurements, lead trade studies, collaborate across engineering teams, mentor engineers, and contribute to patents.

Own calibration architecture, algorithms, system integration, laboratory bring-up, and verification for an optical vector-matrix multiplication engine. Develop control and optimization methods for optical phase, amplitude, and timing calibration; specify calibration hardware and software interfaces; lead hardware characterization and debug; correlate measurements with models; define diagnostics and verification plans; and mentor engineers. The role requires extensive hands-on work with electro-optic or mixed-signal systems, test equipment, automated measurement software, and cross-functional design teams.

Leads design verification methodology and team development for complex compute ASICs. Owns UVM testbench architecture, multi-level verification planning, VIP integration, gate-level simulation, FPGA-based verification, cloud-hosted emulation, formal verification, coverage closure, and AI-assisted testbench development. Partners across architecture, RTL, physical design, DFT, and validation to drive tapeout readiness.

Lead the end-to-end electronic IC program from architecture and specification through ASIC design, verification, tapeout, post-silicon bring-up, and production readiness. Coordinate internal engineering teams and external foundry, IP, OSAT, and design-service partners. Own schedules, dependencies, risks, readiness reviews, tapeout logistics, lab bring-up, silicon debug, and executive reporting. Establish AI-augmented program processes and drive cross-functional execution for a first-silicon mixed-signal ASIC supporting optical AI compute.

Model the architecture and performance of an optical AI inference accelerator through hardware/software co-design. Responsibilities include bringing up transformer and other AI workloads, integrating Hugging Face and PyTorch models, developing Python and C++ functional, performance, energy, and power models, conducting roofline and limiter analyses, modeling memory and compute blocks, simulating RTL, and maintaining reproducible tests, configurations, plots, and reports.

Build functional, performance, energy, power, and area models for AI accelerator workloads and hardware/software co-design. Bring up PyTorch and Hugging Face workloads, model optical GEMM, memory systems, tiling, scheduling, ISA, NoC traffic, and multi-chip mapping. Develop Python analytical models and bit-accurate C++ simulations, contribute to event-driven simulation infrastructure, correlate models with RTL through Verilator and SystemVerilog, establish modeling methodology, and mentor engineers.

Own performance and energy benchmarking for an optical AI inference accelerator. Build reproducible benchmarks across analytical models, architecture models, RTL simulation, and competitor GPUs. Bring up workloads from Hugging Face, PyTorch, papers, and inference stacks; measure latency, throughput, power, and energy; analyze bottlenecks; operate cloud or lab environments; and document configurations, logs, assumptions, and discrepancies.

Lead integration of full-chip or major SoC subsystems, owning top-level flows and cross-domain decisions across DFT, power, timing, and interconnect architecture. Partner with architecture, RTL, physical design, verification, and DFT teams to resolve system tradeoffs. Support organizational growth through hiring and mentoring while remaining hands-on with advanced-node, high-bandwidth, low-power chip designs.

Lead end-to-end physical design and SoC implementation from synthesis through tapeout on advanced process nodes. Build and automate synthesis, timing closure, power, clock, physical verification, and IP/library management flows. Integrate analog and mixed-signal components, support new process technologies, and collaborate with RTL, DV, and analog teams. Build, hire, and manage a multi-site physical design organization delivering optimized GDSII implementations for complex SoCs.