EMIR Engineer (Power Integrity)

This role is for one of the Weekday's clients

Min Experience: 2+ years

Location: Bengaluru
JobType: full-time

We are seeking a skilled EMIR Engineer with expertise in Power Integrity analysis for ASIC and SoC designs. In this role, you will be responsible for performing Electromigration (EM) and IR Drop (EMIR) analysis to ensure the reliability, performance, and robustness of advanced semiconductor designs. You will work closely with Physical Design teams to identify, analyze, and resolve power integrity issues while supporting successful design signoff.

This is an excellent opportunity for engineers passionate about semiconductor design, power integrity, and advanced silicon implementation.

• Perform comprehensive Electromigration (EM) and IR Drop (EMIR) analysis for ASIC and SoC designs.
• Analyze and resolve Static IR, Dynamic IR, Signal EM, and Power EM violations.
• Support power integrity signoff by identifying potential reliability risks and implementing effective solutions.
• Collaborate closely with Physical Design engineers to achieve EMIR closure and optimize power delivery networks.
• Perform detailed analysis of power integrity reports and recommend design improvements.
• Validate power grid quality and ensure compliance with design reliability and performance requirements.
• Work with implementation teams to optimize power distribution, reduce voltage drop, and improve electromigration margins.
• Support design closure activities by resolving power integrity issues within project timelines.
• Contribute to continuous improvement of EMIR methodologies, analysis flows, and automation.
• Document analysis results, methodologies, and best practices for future reference.

• 2–5 years of experience in EMIR or Power Integrity analysis.
• Strong expertise in Power Integrity analysis for ASIC/SoC designs.
• Hands-on experience with Static IR Analysis.
• Experience performing Dynamic IR Analysis.
• Strong understanding of Electromigration (EM) analysis.
• Experience analyzing both Signal EM and Power EM violations.
• Hands-on experience with RedHawk-SC.
• Good understanding of the ASIC Physical Design flow.
• Strong analytical and debugging skills for power integrity signoff.

• Experience with power grid design and optimization.
• Knowledge of advanced semiconductor technology nodes.
• Familiarity with physical verification and design signoff methodologies.
• Experience with scripting using TCL, Python, or Perl for automation.
• Understanding of timing closure and low-power implementation techniques.

• Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related field.
• 2–5 years of experience in Power Integrity, EMIR, or ASIC Physical Design.
• Experience supporting full-chip EMIR signoff for complex ASIC or SoC projects.
• Familiarity with industry-standard EDA tools used for physical implementation and signoff.

• Strong analytical and problem-solving abilities.
• Excellent attention to detail and debugging skills.
• Effective communication and collaboration across cross-functional engineering teams.
• Ability to manage multiple priorities in a fast-paced semiconductor development environment.
• Self-motivated with a continuous learning mindset.