E-core CPU Layout Design Engineer

Posted Yesterday
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Penang, Daerah Timor Laut, Penang, MYS
In-Office
Expert/Leader
Artificial Intelligence • Cloud • Information Technology • Software
Creating world-changing technology that enriches the lives of every person on earth.
The Role
Design and implement physical layouts for E-Core (Atom) CPU memory compilers and RF IP. Perform transistor- and cell-level planning, layout, assembly, routing, DFM/verification, IR drop and reliability analysis, and collaborate with design automation teams to define methodologies and deliver complex layouts on schedule.
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Job Details:

Job Description: As an E-Core (Atom) CPU Layout Design Engineer, you will be part of a highly skilled team responsible for the design of future generation, high-performance Intel Atom microprocessors. In this role, you will drive the physical implementation of a variety of memory compilers and RF custom IP blocks that directly support Intel's CPU products. You will work in a dynamic environment where design challenges are complex, assignments are broadly defined, and solutions often require creativity, deep technical knowledge, and strong problem-solving skills. Your responsibilities will include, but will not be limited to: - Hands on experience with layouts of memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc. in compiler context - Actively bridges the gap between circuit engineering, design automation and mask design. The layout work required encompasses transistor/device and cell level planning, layout, assembly and routing. - Expected to be productive and proficient in all aspects of layout - this includes Computer Aided Design (CAD) tool utilization (layout editing/verification/Design for Manufacturing (DFM)/quality), productivity macro usage, and solid understanding of all related methodologies and workflow models. - Expected to provide engineering judgment to key decision making and design trade-offs. Examples include IR drop analysis and resolution, Reliability Verification (RV. Electromigration and Self Heat) analysis and resolution, ECO assessment for feasibility, effort, risk, schedule analysis. - Drive methodology definition and refinement for memory compilers. This entails working in conjunction with the Design Automation (DA) teams closely, and senior/principal design engineers to perform problem exploration, feasibility studies, analyze options, and establish and implement recommendations. - Independently assess and plan complex layout assignments and derive a realistic schedule to execute to and deliver on time. In addition to the qualifications below the ideal candidate will also have the following: -Excellent verbal and written communication skills. -Excellent interpersonal skills. -Prioritization and multitasking skills. -Good analytical and problem-solving skills

Qualifications:Minimum Qualifications: - Candidate must possess a Bachelor's or Master's degree in Electronic/Microelectronic Engineering, Computer Engineering, or a related engineering discipline. - 10+ years of experience in layout design. - Proficient Programming skills (UNIX shell script, Tcl, Perl)

          

Job Type:Experienced Hire

Shift:Shift 1 (Malaysia)

Primary Location: Malaysia, Penang

Additional Locations:

Business group:Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Skills Required

  • Bachelor's or Master's degree in Electronic/Microelectronic Engineering, Computer Engineering, or related engineering discipline
  • 10+ years of experience in layout design
  • Hands-on experience with layouts of memory building blocks (control, sense amplifiers, I/O blocks, bit cell array, decoders) in compiler context
  • Proficient programming skills: UNIX shell script, Tcl, Perl
  • Proficient use of CAD tools for layout editing, verification, DFM and quality workflows
  • Experience bridging circuit engineering, design automation and mask design; transistor/device and cell level planning, assembly and routing
  • Ability to perform IR drop analysis, reliability verification (electromigration, self-heat) and assess ECO feasibility, effort, risk and schedule
  • Experience driving methodology definition and refinement for memory compilers in conjunction with DA teams
  • Excellent verbal and written communication, interpersonal, prioritization and multitasking skills

Intel Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.

  • Parental & Family Support Family-building and caregiving supports are extensive, including fertility coverage, adoption assistance, paid parental leave, childcare and elder care resources, and a structured reintegration for new parents. These benefits are positioned as best-in-class elements of the package.
  • Leave & Time Off Breadth Time off includes generous PTO, a paid sabbatical after extended tenure, and multiple leave types such as family, medical, bereavement, and military. This breadth enables employees to disconnect, recharge, and manage life events.
  • Retirement Support Long-term savings are bolstered by a competitive 401(k) match and access to deferred compensation for eligible levels, alongside stock purchase opportunities. These programs are highlighted as strong tools for financial security.

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HQ: Santa Clara, CA
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Year Founded: 1968

What We Do

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