As an E-Core (Atom) CPU Layout Design Engineer, you will be part of a highly skilled team responsible for the design of future generation, high-performance Intel Atom microprocessors. In this role, you will drive the physical implementation of a variety of memory compilers, custom IP blocks, and layout partitions that directly support Intel's CPU products.
You will work in a dynamic environment where design challenges are complex, assignments are broadly defined, and solutions often require creativity, deep technical knowledge, and strong problem-solving skills.
Your responsibilities will include, but will not be limited to:
- Independently assess and drive complex digital physical design assignments across multiple design stages.
- Work closely with circuit design engineers to interpret schematics and drive physical implementation.
- Work interactively and proactively with our CAD team to debug tool functionality and bugs.
- Build and verify all levels of physical design hierarchy from leaf-level cell layout to block-level and top-level integration.
- Partnering with SoC teams and cross site design groups to ensure alignment, reuse, and consistency across projects.
In addition to the qualifications below the ideal candidate will also have the following:
-Excellent verbal and written communication skills.
-Excellent interpersonal skills.
-Prioritization and multitasking skills.
-Good analytical and problem-solving skills
Minimum Qualifications:
- Candidate must possess a Bachelor's or Master's degree in Electronic/Microelectronic Engineering, Computer Engineering, or a related engineering discipline.
- 3+ years of experience in layout design.
Additional qualifications include:
- less than 2 years of experience in layout design for grade 3.
- Familiarity with Very Large Scale of Integration VLSI and Complementary Metal-Oxide Semiconductor (CMOS) logic circuit design.
- Proficient programming skills UNIX shell script TCL Perl.
Job Type:Experienced HireShift:Shift 1 (Malaysia)Primary Location: Malaysia, PenangAdditional Locations:Malaysia, KulimPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- Bachelor's or Master's degree in Electronic Engineering, Microelectronic Engineering, Computer Engineering, or a related engineering discipline
- 3 or more years of experience in layout design
- Less than 2 years of layout design experience for grade 3 consideration
- Familiarity with Very Large Scale Integration (VLSI) and CMOS logic circuit design
- Programming proficiency in UNIX shell scripting, Tcl, and Perl
- Excellent verbal and written communication skills
- Excellent interpersonal skills
- Prioritization and multitasking skills
- Good analytical and problem-solving skills
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
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Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
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Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
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Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
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