E-Core (Atom) CPU Layout Design Engineer

Posted Yesterday
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2 Locations
In-Office
Mid level
Artificial Intelligence • Cloud • Information Technology • Software
Creating world-changing technology that enriches the lives of every person on earth.
The Role
Designs physical layouts for Atom CPU memory compilers, custom IPs, analog blocks, digital designs, and partitions. Responsibilities include array planning, area optimization, critical wire analysis, layout verification, SoC integration, reliability checks, autorouter and placer use, methodology improvement, circuit feasibility assessment, troubleshooting, and cross-site collaboration.
Summary Generated by Built In
Job Details:

Job Description: The Role and Impact: As an E-Core (Atom) CPU Layout Design Engineer, you will play a pivotal role in shaping the physical layout of Intel's cutting-edge Atom processors, contributing to high-performance products that drive a wide range of applications. In this role, you'll focus on implementing custom layouts for analog blocks, digital designs, and memory compilers, ensuring compliance with design specifications and reliability criteria. Your work will directly impact Intel's ability to deliver innovative microprocessor solutions to the market. Business Group: Join Intel Corporation's Atom Layout Design team, a group dedicated to advancing Intel Atom processors (E-Core), which power a diverse array of products spanning entry-level PCs, smartphones, laptops, and IoT devices. This team plays a crucial role in supporting Intel's mission to deliver high-performance, energy-efficient solutions that drive technological innovation and global connectivity. Key Responsibilities: - Drive custom layout design for memory compilers, custom IPs, and partitions supporting CPU products. - Perform physical array planning, area optimization, and critical wire analysis to ensure efficient designs. - Conduct complete layout verification, including design rule compliance, SoC integration standards, and reliability checks such as electron migration, voltage drop (IR), and self-heating. - Utilize custom autorouters and placers for layout construction while innovating new methods to improve productivity and design quality. - Collaborate closely with circuit design engineers to assess feasibility, provide feedback, and implement circuit enhancement requests. - Troubleshoot design, tool flow, and methodology issues to ensure seamless implementation and integration. - Partner with cross-site teams to align on design strategies, reuse methodologies, and project consistency.

Qualifications:Minimum Qualifications: - Bachelor's or Master's degree in Electronics/Microelectronics Engineering, Computer Engineering, or a related discipline with 3+ years of hands-on experience in physical design, demonstrated through internships, academic projects, coursework, or hands-on training. - Proficiency in Very Large Scale Integration (VLSI) and Complementary Metal-Oxide Semiconductor (CMOS) logic circuit design. - Programming skills in UNIX shell scripting, TCL, and Perl. Preferred Qualifications: - Strong ability to analyze and solve complex technical problems independently. - Excellent communication, interpersonal, and multitasking skills, with a demonstrated ability to collaborate across functions and teams. - Prior experience developing innovative layout methodologies and improving design workflows. Consider joining us to contribute your expertise to ground-breaking designs that shape the future of technology. Apply now and become part of a team where your creativity and skills will drive meaningful impact.

          

Job Type:Experienced Hire

Shift:Shift 1 (Malaysia)

Primary Location: Malaysia, Penang

Additional Locations:Malaysia, Kulim

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Skills Required

  • Bachelor’s or Master’s degree in Electronics Engineering, Microelectronics Engineering, Computer Engineering, or a related discipline
  • 3+ years of hands-on experience in physical design, demonstrated through internships, academic projects, coursework, or hands-on training
  • Proficiency in VLSI and CMOS logic circuit design
  • Programming skills in UNIX shell scripting, TCL, and Perl
  • Ability to analyze and solve complex technical problems independently
  • Excellent communication, interpersonal, and multitasking skills
  • Ability to collaborate across functions and teams
  • Experience developing innovative layout methodologies and improving design workflows

Intel Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.

  • Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
  • Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
  • Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.

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The Company
HQ: Santa Clara, CA
75,000 Employees
Year Founded: 1968

What We Do

Our mission is to shape the future of technology to help create a better future for the entire world, that’s the power of Intel Inside. With more ingenuity and creativity inside, our work is at the heart of countless innovations. From major breakthroughs to things that make everyday life better— they’re all powered by Intel technology. With a career at Intel, you can help make the future more wonderful for everyone.

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