ASIC Design Engineering Director / Sr. Manager

Job Description  

We are seeking a ASIC Design Engineering Director / Sr. Manager to lead the microarchitecture, RTL implementation, and front-end development of high-performance connectivity solutions for next-generation network controllers. The ideal candidate has deep expertise in front-end ASIC design, strong leadership experience, and a solid understanding of communication and interface standards such as PCIe, Ethernet, UALink.This role requires on-site presence.

Basic Qualifications:  

• Bachelor’s degree in Electrical or Computer Engineering required; Master’s degree preferred.
• 12+ years of experience developing or supporting complex SoC/silicon products for server, storage, or networking applications.
• 5+ years of technical leadership or engineering management experience.
• Strong professional presence with the ability to manage multiple priorities, prepare for and lead customer discussions, and operate independently with minimal supervision.
• Entrepreneurial, open-minded, and action-oriented mindset with a strong customer focus.
• Authorized to work in the U.S. and able to start immediately.

Required Experience:  

• Strong front-end design expertise in high-speed digital logic design in ASICs/SOCs, including architecture, RTL development, simulation, synthesis, timing closure, GLS, and DFT.
• Hands on experience in guiding and mentoring design engineers throughout the chip front end development
• hands-on experience in Micro architecture and timing closure for high-speed logic design ( 1-2GHz) in advanced process nodes
• Hands-on experience and working knowledge of Ethernet or UALink and  Familiarity with other high-speed interconnect protocol
• Proven experience with packet/cell based high-speed switching architectures, cross bars, and high-speed interconnects.
• Demonstrated ownership of full-chip or block-level development from architecture through GDS, delivering multiple complex designs into production, working closely with both hardware and software teams.
• Experience with Cadence and/or Synopsys digital design and DFT flows
• Expertise in IP/SOC integration
• Expertise in silicon bring-up, performance tuning, and lab debug 

Preferred Experience:  

• Proficiency in scripting languages such as Python or equivalent.
• Background in developing ASIC design methodologies and driving methodology adoption across teams. 

This position can be hired as a Senior Manager Level or Director Level. The base salary range is $230,000 USD – $265,000 USD. Your base salary will be determined based on location, experience, and employees' pay in similar positions.