As a Sr. SoC Design Verification Engineer, you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology. Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable effective verification. Coordinate cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan. Using system full application to verify performance and identify short falls.
Responsibility
Pre-silicon system verification. This include SoC, FPGA & Full Chip design verification.
Create testcase and testbench with UVM methodology
Fullchip/system functional verification, by defining verification strategies/methodology and test plan to enable effective verification
Coordinate/interface cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan
Experience on Emulation will be an add on.
5+ years of experience with complex ASIC designs and/or verification
Familiar with System Verilog language
Experience on UVM verification methodology, and formal verification method
Working knowledge of scripting in Linux/ Unix environments as well as proficiency in Perl and or Python is desirable.
Experience with Design for Debug (JTAG, High speed USB, PCIe based debug, Visualization of Internal Signal) architecture and design verification of same.
Experience with ARM and RISC Debug Architectures is desired with focus on design verification.
Any prior working experience on UltraSoC/ Tessent Embedded Analytics Debug Architecture will be a plus but not must for this position.
Strong communication skills and the ability to work with a team spread across different geography sites
Flexible in dynamic environment
Skills Required
- 5+ years of experience with complex ASIC designs and/or verification
- Familiarity with SystemVerilog
- Experience with UVM verification methodology
- Experience with formal verification methods
- Working knowledge of scripting in Linux/Unix environments
- Proficiency in Perl and/or Python
- Experience with Design for Debug (JTAG, High-speed USB, PCIe based debug, visualization of internal signals) architecture and verification
- Experience with ARM and RISC debug architectures
- Experience with emulation
- Prior experience with UltraSoC or Tessent Embedded Analytics debug architectures
- Strong communication skills and ability to work with geographically distributed teams
- Ability to work in a flexible, dynamic environment
Altera (altera.com) Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Altera (altera.com) and has not been reviewed or approved by Altera (altera.com).
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Retirement Support — Feedback suggests retirement programs are robust, with offerings such as a 401(k) and a pension. This breadth supports long-term financial security.
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Leave & Time Off Breadth — Feedback suggests time-off policies are generous, including PTO, paid sick days, and paid holidays. Wellness initiatives like gym memberships further support balance.
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Parental & Family Support — Feedback suggests parental leave is generous. Family-building support, including fertility benefits and adoption reimbursement, is highlighted as part of the package.
Altera (altera.com) Insights
What We Do
Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.
