About the job
We are seeking a skilled Design for Test (DFT) Principal Engineer to join our team. This role is pivotal in ensuring the testability and manufacturability of our ASIC/SoC products designed for the automotive, Industrial & Consumer applications. The ideal candidate will have extensive experience in DFT methodologies and will lead a team of engineers to develop robust test strategies that meet industry standards.
ResponsibilitiesKey Responsibilities:
DFT Strategy Development: Design and implement DFT methodologies for ASIC/SoC products, focusing on automotive/industrial/consumer applications to ensure high quality and reliability.
Architecture Design: Collaborate with hardware and software teams to integrate DFT features into the product architecture, ensuring compatibility with testing standards.
Team Leadership: Lead & manage a team of DFT engineers, providing mentorship and technical guidance to enhance their skills and capabilities.
Test Planning: Develop comprehensive test plans, including ATPG, BIST, and scan insertion strategies, to optimize fault coverage and reduce test costs.
Collaboration: Work closely with design, validation, test and manufacturing teams to align DFT strategies with overall product goals and requirements.
Quality Assurance: Establish metrics and benchmarks for DFT processes, and ensure compliance with automotive industry standards (e.g., ISO 26262).
Tool Development: Evaluate and implement DFT tools and methodologies to improve test efficiency and effectiveness.
Continuous Improvement: Stay updated with industry trends and technologies in DFT and automotive testing, driving innovation within the team.
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
12+ years of experience in DFT for ASIC/SoC design, with a strong background in automotive applications.
Proven experience leading DFT teams and managing complex projects.
Experience in post silicon debug, yield improvement and On-field failure (EFAR) debug.
In-depth knowledge of DFT techniques such as scan design, boundary scan, BIST, and fault simulation.
Familiarity with automotive industry standards and regulations (e.g., ISO 26262).
Proficiency in using DFT tools and EDA software.
Strong problem-solving skills and ability to work collaboratively in a fast-paced environment.
Excellent communication skills, both verbal and written.
More details about our company benefits can be found here:
https://www.onsemi.com/careers/career-benefits
Skills Required
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
- 12+ years of experience in DFT for ASIC/SoC design
- Proven experience leading DFT teams and managing complex projects
- Experience in post silicon debug, yield improvement and On-field failure debug
- In-depth knowledge of DFT techniques such as scan design, boundary scan, BIST, and fault simulation
- Familiarity with automotive industry standards and regulations (e.g., ISO 26262)
- Proficiency in using DFT tools and EDA software
- Strong problem-solving skills and ability to work collaboratively in a fast-paced environment
- Excellent communication skills, both verbal and written
What We Do
We are building a better future through intelligent technology. For over 60 years, onsemi and its ancestors have been leading the world’s greatest technology advancements. onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.
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