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The Role
Design, implement, validate, and debug DFT solutions (TAP/JTAG, IJTAG, BSCAN, MBIST, ATPG, scan compression) across IP and SoC. Drive test access, pattern generation, coverage optimization, memory test validation, silicon debug, RTL and gate-level validation, and cross-team DFT integration and signoff.
Summary Generated by Built In
Job Details:Job Description:
- Design, implement, validate, and debug Design-for-Test (DFT) solutions to ensure manufacturability, test coverage, and silicon quality across IP and SoC programs.
- Responsibilities include development and validation of TAP/JTAG and IJTAG infrastructures, Boundary Scan (BSCAN), MBIST, Scan/ATPG methodologies, and associated test collateral such as ICL, PDL, BSDL, and ATPG patterns. The role requires driving test access, pattern generation, coverage optimization, memory test validation, and debug of scan, at-speed, and silicon bring-up issues while ensuring robust DFT integration across the product lifecycle.
- The engineer collaborates closely with Design, Verification, Physical Design, Product Engineering, Manufacturing Test, and IP teams to ensure DFT readiness and signoff.
- Key responsibilities include RTL and Gate-Level Simulation (GLS) validation, root-cause analysis and resolution of DFT-related failures, adoption of DFT methodologies and best practices, and leadership of technical reviews and continuous process improvements.
- Required expertise includes TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (IEEE 1149.1), MBIST, Scan Compression, ATPG, Verilog/System Verilog, Tcl/Perl/Python scripting, DFT verification, silicon debug, and strong communication and technical leadership skills.
- Candidate must have a Bachelor's Degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or related field with 10+ years of experience Or
- Master's Degree in Electrical Engineering, Microelectronics, VLSI or related field with 8+ years of experience.
- Scan Insertion, DFT features, RTL design for DFT and verification.
Job Type:Experienced HireShift:Shift 1 (India)Primary Location: India, BangaloreAdditional Locations:Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- Bachelor's in EE/Elec/CompEng/Computer Science with 10+ years OR Master's in EE/Microelectronics/VLSI with 8+ years experience
- Expertise with TAP/JTAG infrastructure and Boundary Scan (IEEE 1149.1)
- Experience with IJTAG (IEEE 1687) and related infrastructures
- MBIST design and memory test validation experience
- Scan insertion, scan compression, and RTL design for DFT
- ATPG methodologies, pattern generation, and ATPG pattern handling
- Familiarity with ICL, PDL, BSDL and test collateral generation
- Verilog and SystemVerilog for DFT implementation and validation
- Scripting skills: Tcl, Perl, Python for automation and tooling
- RTL and Gate-Level Simulation (GLS) validation and DFT verification
- Silicon debug, root-cause analysis of DFT-related failures and at-speed issues
- Strong communication, cross-functional collaboration, and technical leadership
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
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Parental & Family Support — Family-building and caregiving supports are extensive, including fertility coverage, adoption assistance, paid parental leave, childcare and elder care resources, and a structured reintegration for new parents. These benefits are positioned as best-in-class elements of the package.
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Leave & Time Off Breadth — Time off includes generous PTO, a paid sabbatical after extended tenure, and multiple leave types such as family, medical, bereavement, and military. This breadth enables employees to disconnect, recharge, and manage life events.
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Retirement Support — Long-term savings are bolstered by a competitive 401(k) match and access to deferred compensation for eligible levels, alongside stock purchase opportunities. These programs are highlighted as strong tools for financial security.
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What We Do
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