Hi,
Job Title: Design Verification Engineer (UVM)
Location: Sunnyvale, CA
Duration: Long Term contract
Mandatory Skill: Strong hands-on UVM expertise is a MUST.
Job Summary: We are looking for an experienced Design Verification Engineer with strong expertise in SystemVerilog and UVM (Universal Verification Methodology) to develop and execute verification environments for complex semiconductor designs. The ideal candidate should have hands-on experience in functional verification, testbench development, debugging, and coverage closure.
Key Responsibilities :
Develop and maintain reusable UVM-based verification environments.
Create and implement test plans, test scenarios, and verification strategies.
Develop constrained-random and directed test cases using SystemVerilog.
Build and maintain UVM components, including agents, drivers, monitors, sequencers, and scoreboards.
Develop assertions using SystemVerilog Assertions (SVA).
Perform functional, code, and assertion coverage analysis.
Debug simulation failures and identify design or testbench issues.
Work closely with RTL designers and architecture teams to understand design specifications.
Drive functional coverage closure and achieve verification sign-off.
Participate in design reviews, verification planning, and regression analysis.
Automate verification tasks using scripting languages such as Python, Perl, or Shell.
Required Skills
Strong hands-on experience in UVM-based functional verification.
Excellent knowledge of SystemVerilog.
Experience developing reusable UVM testbenches from scratch.
Strong understanding of OOP concepts and constrained-random verification.
Experience with UVM sequences, sequencers, drivers, monitors, agents, and scoreboards.
Hands-on experience with SystemVerilog Assertions (SVA).
Knowledge of functional coverage and code coverage.
Experience with simulation and debugging tools such as:
Synopsys VCS
Cadence Xcelium
Siemens Questa
Strong debugging and problem-solving skills.
Good understanding of digital design concepts and RTL verification methodologies.
Additional Information
All your information will be kept confidential according to EEO guidelines.
Skills Required
- Strong hands-on experience in UVM-based functional verification
- Excellent knowledge of SystemVerilog
- Experience developing reusable UVM testbenches from scratch
- Strong understanding of object-oriented programming concepts and constrained-random verification
- Experience with UVM sequences, sequencers, drivers, monitors, agents, and scoreboards
- Hands-on experience with SystemVerilog Assertions
- Knowledge of functional coverage and code coverage
- Experience with Synopsys VCS, Cadence Xcelium, or Siemens Questa
- Strong debugging and problem-solving skills
- Good understanding of digital design concepts and RTL verification methodologies
What We Do
Cystems Logic is gaining a competitive edge in today's economy and its all about speed and flexibility. Companies of small to large size and complexity need to adapt swiftly to evolving global business trends and opportunities. Cystems Logic supports rapid innovation to drive your business process excellence for increased productivity and profitability. We are here to lower to cost of using costly technology at increase Return on Investment (ROI). Our Strength is our talented team with solid foundation in the ERP arena. We are emerging providers of SAP new implementation, maintenance & support for small to large size companies in specific industry domain.
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