Sr Principal Design Engineer

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.

Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Title: Sr Principal Design Engineer

Location: Cambridge, United Kingdom

Reports to: Software Engineering Director

Job Overview:

Genus Synthesis Solution is a leading technology tool for synthesizing digital designs from RTL (Register Transfer Language) specifications (Verilog or VHDL) into netlists based on standard cells. Trusted by over 400 customers worldwide, Genus enables chip design through cutting-edge optimization for timing, area, and power.

Genus is complemented by ChipWare®, an IP library of configurable, off-the-shelf components that deliver best-in-class hardware quality across power, area, and delay requirements.

As part of our expansion, we are seeking talented individuals who share our passion for computer arithmetic and our commitment to quality, innovation, and insight. This role offers a unique opportunity to work across software and hardware development, applied research, and direct customer engagement, making you a true subject matter expert in the field.

Job Responsibilities:

• Collaborate within a team to design, optimize, verify, and document a library of high-quality arithmetic components (e.g., floating-point operators) for chip designers.
• Ensure components are robust, efficient, and easy to integrate.
• Define and maintain architectural standards for software and hardware integration.
• Partner with internal and external stakeholders to capture requirements and translate them into technical specifications.
• Drive innovation in system design and optimization for timing, area, and power.

Job Qualifications:

• Strong academic background (Bachelor’s or Master’s in computer science, Software Engineering, Mathematics, Physics, or Electrical Engineering. (PhD is a plus)
• Proven experience in hardware design with (System)Verilog.
• Solid programming skills in C++, Java, or Python; experience with scripting languages (e.g., TCL) is a plus.
• Expertise in system design.
• Familiarity with formal verification and design verification methodologies.
• Knowledge of floating-point arithmetic and numerical computation is advantageous.
• Hands-on experience with simulation tools, modelling, and performance optimization.
• Excellent analytical and creative problem-solving skills.
• Strong communication skills and ability to interface with internal and external stakeholders.

Check what we can offer you:

• Competitive salary
• 25 days holiday per year
• Private Medical and Dental plans, Income Protection and Life Insurance
• Group Personal Pension Plan
• Cycle to work scheme and gym subsidy
• 5 days paid time to volunteer to give back to our communities
• Employee Stock Purchase Plan
• The opportunity to work for a Great Place to Work© & Fortune 100 organization

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.