The role will be a key player in organization responsible for Characterizing and validating Analog and Digital IP based Silicon Solutions at Cadence.
Candidate should possess strong leadership skills with ability to manage multiple priorities and guide team members on day-to-day lab tests and silicon characterization activities. Ownership of tasks, ability to collaborate with remote teams located worldwide and clear communication skills, are must have attributes in this role. Coordination with R&D, Marketing teams in defining the scope and delivering the results in time are critical.
Minimum Qualifications & Professional Experience:
• 2-10years (with BTech) or 10 years (with MTech) experience in Post-Silicon PHY, Systems Interop and Compliance testing.
• 5-7 years of management experience leading/mentoring a small team of engineers
• Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on Ethernet/PCIe/CXL/UCIe/
• Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers.
- Proficient with Ethernet, PCIe, UCIe standards and Protocols. Proven experience to interpret the standard’s specification to develop Electrical and Protocol, Interoperability and Compliance test suites to validate the silicon.
- Ability to isolate the PHY and controller (MAC/PCS) features to test, develop calibration / compliance lab suites and characterize.
- Architect and design Printed circuit boards in Schematic and layout level. Familiarity with peripheral chips, high speed interface design techniques, Signal and Power integrity checks / analysis and fixes needed to meet the performance requirements.
- Experience in PCIe/UCIe LTSSM states / UCIe Interfaces / Ethernet standards is a plus.
- Proven experience in developing lab automation scripts and test result analysis to debug and root cause silicon failures.
- Expertise in developing ESD/Latchup/ HTOL tests to meet industry standards reliability qualification & specification
- Expert level knowledge in Verilog RTL coding for FPGA, python,C/C++
Skills Required
- 2–10 years of experience with a BTech or 10 years with an MTech in post-silicon PHY, systems interoperability, and compliance testing
- 5–7 years of experience managing, leading, or mentoring a small engineering team
- Physical-layer and protocol-layer experience with at least one high-speed SerDes interface, such as Ethernet, PCIe, CXL, or UCIe
- Debugging experience using oscilloscopes, bit error rate testers, protocol exercisers, and analyzers
- Proficiency with Ethernet, PCIe, UCIe standards and protocols
- Experience interpreting specifications and developing electrical, protocol, interoperability, and compliance test suites
- Ability to isolate PHY and controller features for testing, calibration, compliance, and characterization
- Experience architecting and designing printed circuit boards at schematic and layout levels
- Familiarity with peripheral chips, high-speed interface design, signal integrity, and power integrity analysis
- Experience developing lab automation scripts and analyzing test results to debug and root-cause silicon failures
- Expertise developing ESD, latch-up, and HTOL tests for industry reliability standards
- Expert-level Verilog RTL coding knowledge for FPGA development
- Experience with Python, C, and C++
- Experience with PCIe/UCIe LTSSM states and UCIe interfaces
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
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Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
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Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
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Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
Cadence Design Systems Insights
What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
