CPU Design Verification Engineer

Job Details:

Job Description: 

Who We Are

We are working on the CPU design in Folsom. The team in Folsom has the frontend team working on ucode, RTL and validation. We also have a backend team working on circuit design, structural design, low power design. Finally, we have a backend integration working on full-chip timing, layout and design integration.

Who You Are

This role is in CPU Design Verification Engineering Intern. Your responsibilities will include, but are not limited to:

• In this role you will work closely with both design and silicon and develop a strong knowledge and understanding of Intel's microarchitecture and of Intel's silicon testing process.

• You will make significant contributions to design, development, and validation of testability circuits.

• You will be involved in the evaluation, development, and debug of complex test methods.

• You will analyze fault grade models of microprocessors for functional coverage gaps, work with the design RTL, micro-architecture specifications, and designers to intricately understand the details of the design in order to develop test strategies for low coverage logic.

• You will write and debug assembly level functional tests to ensure high test coverage of Intel's microprocessors and prevent silicon defects from reaching our customers and help design new DFT features to enhance functional testability of Intel microprocessors.

Qualifications:

You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
 

Minimum Qualifications

• The candidate must be currently taking Master’s Degree in Electrical or Computer Engineering/Computer Science

Preferred Qualifications

The candidate should have at least 3+ months’ coursework experience exploring the following subjects:

• Computer Architecture

• Hardware description languages (Verilog, VHDL, etc.)

• Programming/scripting languages (C, C++, Csharp, Java, PERL, Python, etc.)

• Instruction Set Architecture (IA32, MIPS, etc.)

• Logic design

          

Job Type:Student / Intern

Shift:Shift 1 (United States of America)

Primary Location: US, Oregon, Hillsboro

Additional Locations:

Business group:The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

Annual Salary Range for jobs which could be performed in the US:

$63,000.00-$166,000.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.