Compute Verification Lead

Posted 15 Days Ago
Be an Early Applicant
Mountain View, CA, USA
In-Office
120K-600K Annually
Senior level
Artificial Intelligence • Hardware • Software
The Role
Senior individual-contributor owning end-to-end verification strategy for compute datapath across UVM/SystemVerilog, assertion-based, formal, and Rust-based software-silicon co-simulation. Mentor verification engineers, set methodology, drive test plans and sign-off from block to SoC, build verification infrastructure, and collaborate with architecture, design, formal, and software teams toward tapeout.
Summary Generated by Built In

What MatX Is Building

MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies.

This is a senior, hands-on individual-contributor (IC) technical leadership role. You will own the verification strategy for the compute datapath and drive it across two complementary worlds: conventional silicon verification (SystemVerilog/UVM, assertion-based, formal) and Rust-based software–silicon co-simulation. You will set direction, raise the bar on quality and coverage, and provide technical guidance to verification engineers working in both styles — including early-career engineers growing into independent owners.

What You'll Do Here
  • Own and drive the end-to-end verification strategy — across block, subsystem, and SoC levels — spanning conventional (UVM/SV, assertion-based, formal) and Rust SW–silicon co-simulation approaches
  • Provide technical direction and mentorship to verification engineers working in both conventional silicon-verification and Rust co-simulation roles; grow early-career engineers into independent owners of their areas
  • Make and own the methodology calls — where conventional UVM/SV, Rust co-simulation, and formal each fit best — and drive verification strategy accordingly
  • Drive verification across the seams: partner with SoC integration, formal verification, and the software/modeling team to turn architectural specifications into concrete, testable properties and coverage closure
  • Plan and drive intermediate and sign-off reviews on test plans, execution progress, and verification closure toward design freeze and tapeout
  • Build and curate verification infrastructure and regressions the broader team can adopt and extend
Who You Are
  • 8+ years of silicon verification experience, including at least one tapeout owning a block's or subsystem's verification — concept-to-silicon experience driving verification from an architecture and/or design specification to production silicon
  • Strong software aptitude, with proven experience crossing language boundaries while driving verification goals — comfortable working across Rust, Python, and C/C++ as the task demands
  • Deep, hands-on expertise in conventional verification — SystemVerilog/UVM, assertion-based verification — with comfort across both formal and simulation-based verification
  • Able to lead across methodologies: you can guide engineers in conventional silicon verification and in Rust-based SW–silicon co-simulation, and set strategy that applies each where it fits
  • Either prior experience verifying designs expressed in abstracted / high-level HDLs (Bluespec, Chisel, etc.), or the ability to ramp quickly on Bluespec and drive verification strategy for designs written in it
  • Strong leadership and communication — you drive sign-off conversations, mentor engineers, and partner cleanly across architecture, design, SoC, and software
Bonus Points If You Have
  • 10+ years of silicon verification experience
  • Experience with the numerics of compute / matrix / vector-math datapaths (floating-point pipelines included) — enough to hold substantive conversations with architects
  • Production Rust experience, or experience standing up Rust-based co-simulation / co-verification flows
  • Hands-on experience in an abstracted / functional HDL ecosystem (Bluespec BH/BSV, Chisel, etc.)
  • Familiarity with emulation and prototyping platforms; participation in silicon debug and bring-up
  • Background in AI accelerator, GPU/TPU-class, or other high-throughput compute datapath verification

Compensation

The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job related skills, and relevant education and training. Career length is only a guideline for compensation.

  • Early Career - $120,000 - $275,000 + equity
  • Mid Career - $175,000 - $450,000 + equity
  • Senior Career - $275,000 - $600,000 + equity

What We Offer

  • A Stake in our success A cash/equity mix that fits your needs and option to do early exercise
  • Health & Wellness Company subsidized Health, Dental, Vision, and Life insurance; Pre-tax Health Savings Accounts with generous company contribution (even if you don’t)
  • Time To Recharge 4 weeks paid time off (accrued), 12 company holidays, and 3 weeks remote/flexible work per year
  • Support to Parents Up to 12 weeks of paid parental leave, regardless of your path to parenthood
  • Learning & Development $1,500 yearly towards your professional development e.g. conferences, courses, and other learning opportunities
  • Team Connection Team Lunches, quarterly off-sites, and regular town halls
  • Financial Wellbeing 401K and/or Roth IRA, with 5% company contribution, even if you don’t!
  • Flexible Spending Accounts Pre-tax spend accounts for medical, dental/vision, dependent care, parking, and transit expenses
  • Commute On Us For those commuting up to 1 hour, put your rideshare cost on our company card and reclaim the drive-time to get work done!
  • MatX E[x]tras $50 per month to use on the perks you care about most 
  • Remote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi expense reimbursement

As part of our dedication to the diversity of our team and our focus on creating an inviting and inclusive work experience, MatX is committed to a policy of Equal Employment Opportunity and will not discriminate against an applicant or employee on the basis of race, color, religion, creed, national origin or ancestry, sex, gender, gender identity, gender expression, sexual orientation, age, physical or mental disability, medical condition, marital/domestic partner status, military and veteran status, genetic information or any other legally recognized protected basis under federal, state or local laws, regulations or ordinances.

All candidates must be authorized to work in the United States and work from our offices in Mountain View Tuesdays-Thursdays.

This position requires access to information that is subject to U.S. export controls. This offer of employment is contingent upon the applicants capacity to perform job functions in compliance with U.S. export control laws without obtaining a license from U.S. export control authorities.

MatX does not accept unsolicited resumes from individual recruiters or third-party recruiting agencies in response to job postings. No fee will be paid to third parties who submit unsolicited candidates directly to our hiring managers or People team and any resumes submitted are deemed to be the property of MatX.

Skills Required

  • 8+ years of silicon verification experience
  • At least one tapeout owning a block or subsystem verification (concept-to-silicon)
  • Deep hands-on expertise in SystemVerilog and UVM
  • Experience with assertion-based verification and both formal and simulation-based flows
  • Strong software aptitude and comfort working across Rust, Python, and C/C++
  • Ability to lead and set verification strategy across conventional verification and Rust-based SW-silicon co-simulation
  • Experience with or ability to ramp quickly on abstracted/high-level HDLs (Bluespec, Chisel, etc.)
  • Strong leadership and communication; ability to mentor engineers and drive sign-off
  • Authorized to work in the United States and able to be in Mountain View offices Tuesdays-Thursdays
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The Company
HQ: Mountain View, CA
19 Employees

What We Do

MatX designs hardware tailored for the world’s best AI models: We dedicate every transistor to maximizing performance for large models. For these models, we deliver 10× more computing power, enabling AI labs to make models an order of magnitude smarter and more useful. Our hardware would make it possible to train GPT-4 and run ChatGPT, but on the budget of a small startup. A world with more widely available intelligence is a happier and more prosperous world—picture people of all socioeconomic levels having access to an AI staff of specialist MDs, tutors, coaches, advisors, and assistants.

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