Atom CPU Layout Design Engineer

Posted Yesterday
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Guadalajara, Jalisco, MEX
In-Office
Entry level
Artificial Intelligence • Cloud • Information Technology • Software
Creating world-changing technology that enriches the lives of every person on earth.
The Role
Perform physical layout design for Intel Atom CPU products, including memory compilers, custom IPs, leaf-level cells, and full partition integration. Collaborate with circuit design and cross-functional engineering teams, interpret schematics, and optimize layout scripts, macros, and implementation tools. The role is on-site in Guadalajara and requires permanent unrestricted work authorization in Mexico.
Summary Generated by Built In
Job Details:

Job Description: 

The Role and Impact


As a Layout Design Engineer, you will play a critical role in the physical implementation of next-generation high-performance Intel Atom microprocessors. Your day-to-day responsibilities will include driving the design of memory compilers, custom IPs, and partitions that support CPU products. Your contributions will directly impact the efficiency and performance of Intel's cutting-edge technologies used globally.

 

Business Group


You will join Intel Corporation's ATOM GDC Physical Design organization, which focuses on delivering innovative and efficient physical design solutions for Intel Atom microprocessors. This group supports Intel's broader mission to create world-class semiconductor products that empower cutting-edge computing technologies.



Responsibilities will include but are not limited to:

 

  • Perform and drive complex physical design assignments independently, ensuring best practices and high efficiency.
  • Collaborate closely with circuit design engineers to interpret schematics and enable successful physical implementation.
  • Lead physical design efforts ranging from leaf-level cell design to full partition integration.
  • Assess and implement solutions for custom IPs and memory compilers to support high-performance CPU products.
  • Develop and optimize layout scripts, macros, and tools to enhance design implementation workflows.
  • Work collaboratively with cross-functional teams across various Intel sites to align on design objectives.

 

The ideal candidate should show the following behavioral traits:


  • Good English communication skills.

Qualifications:

Minimum qualifications are required to be initially considered for this position.

 

  • Bachelor's degree in Electronics, Microelectronics Engineering, Computer Engineering, or a related engineering discipline.
  • 6+ months of hands-on experience in layout design, with demonstrated skills gained through internships, academic projects, coursework, or hands-on training.
  • Proficiency with industry-standard layout tools such as Cadence Virtuoso, Synopsys Custom Compiler, or similar software.
  • Advanced English level.

Must have unrestricted, permanent right to work in Mexico (this role is not eligible for visa or immigration sponsorship).

Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.


  • Master's degree in Electronics, Microelectronics Engineering, Computer Engineering, or a related engineering discipline.
  • 1+ year of experience or familiarity with Very Large Scale Integration (VLSI) or Complementary Metal-Oxide-Semiconductor (CMOS) logic circuit design.
  • Practical knowledge of Unix/Linux operating systems.

 Requirements listed would be obtained through a combination of relevant industry job experience, internship experience and/or schoolwork/classes/research.


We invite you to bring your creativity and technical expertise to Intel, where you'll contribute to shaping the future of computing technologies. Your journey starts here-apply today and be part of Intel's innovation legacy.


          

Job Type:Experienced Hire

Shift:Shift 1 (Mexico)

Primary Location: Mexico, Guadalajara

Additional Locations:

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Skills Required

  • Bachelor's degree in Electronics, Microelectronics Engineering, Computer Engineering, or a related engineering discipline
  • At least 6 months of hands-on layout design experience through internships, academic projects, coursework, training, or industry work
  • Proficiency with Cadence Virtuoso, Synopsys Custom Compiler, or similar industry-standard layout tools
  • Advanced English proficiency and good English communication skills
  • Unrestricted, permanent right to work in Mexico
  • Master's degree in Electronics, Microelectronics Engineering, Computer Engineering, or a related engineering discipline
  • At least 1 year of experience or familiarity with VLSI or CMOS logic circuit design
  • Practical knowledge of Unix/Linux operating systems

Intel Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.

  • Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
  • Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
  • Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.

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The Company
HQ: Santa Clara, CA
75,000 Employees
Year Founded: 1968

What We Do

Our mission is to shape the future of technology to help create a better future for the entire world, that’s the power of Intel Inside. With more ingenuity and creativity inside, our work is at the heart of countless innovations. From major breakthroughs to things that make everyday life better— they’re all powered by Intel technology. With a career at Intel, you can help make the future more wonderful for everyone.

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