ASIC Digital Design Engineer

Posted Yesterday
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Pune, Maharashtra, IND
In-Office
Senior level
Cloud • Information Technology • Internet of Things • Professional Services • Software
The Role
Design and integrate RTL for high-performance silicon photonics ASICs and SoCs supporting optical interconnect products. Responsibilities include digital block ownership, mixed-signal and high-speed interface integration, verification collaboration, synthesis, timing closure, power optimization, DFT, automation, debugging, FPGA prototyping, and post-silicon bring-up. The engineer partners across analog, physical design, firmware, packaging, process, ATE, and product engineering teams from architecture through tapeout and production.
Summary Generated by Built In
What You'll DoWe are looking for a talented and experienced Digital Design Engineer to join the Silicon One Optics Group (S1O) Digital Design Team and drive the digital design and integration of Cisco’s silicon photonics integrated circuits for next generation 100G, 200G, and 400G per lambda solutions. In this role, you will own RTL design, and subsystem integration of digital logic used in high-performance optical interconnect products. You will work closely with analog/mixed-signal designers, verification engineers, physical design, DFT, firmware, packaging, process, and product engineering teams to develop robust, high-quality, and manufacturable designs that meet performance, power, reliability, and production requirements. With a strong understanding of digital systems, RTL development, mixed-signal integration, ASIC/SoC design flow, and implementation readiness, you will participate in all phases of digital design from concept through tapeout and production support. You will drive block-level digital development for control functions, interfaces, receive/transmit paths, and integrated high-speed interface circuitry within a silicon photonics module, CPO (Co-Packaged Optics) engine.Specific responsibilities include:·        Own the RTL design of complex digital blocks and subsystems.·        Drive RTL design and integration for control functions, high speed interfaces, and receive/transmit paths.·        Own and review RTL quality, ensuring best practices in coding style, reuse, maintainability, and design robustness.·        Document block-level and top-level design specifications, interface definitions, and implementation plans.·        Work across analog and digital interfaces to ensure seamless mixed-signal integration.·        Collaborate closely with verification teams to define test plans, review coverage, debug issues, and ensure design intent is fully verified.·        Support full-chip integration involving high-speed IPs such as D2D IP, SerDes XSR, and integrated drivers/TIA.·        Support synthesis, timing closure, power optimization, low-power intent, and design-for-test (DFT) considerations.·        Develop scripts and automation flows for analysis, design checks, QoR tracking, and reporting using Python, Perl, Tcl, Shell, or C.·        Independently debug simulation and integration issues and identify root causes of design bugs.·        Support firmware/C coding activities related to CPU subsystem functionality and integration, where needed.·        Contribute to FPGA prototyping and validation activities where applicable.·        Partner with post-silicon and ATE teams on bring-up support, test planning, and production readiness.Who You’ll Work With:

As a Digital Design Engineer, you will work with a diverse team of engineers spanning digital design, analog/mixed-signal design, verification, DFT, physical design, firmware, FPGA, CAD, packaging, and post-silicon validation.


At the concept stage, you will participate in the digital architecture, interface requirements, implementation strategy, and design methodology. During execution, you will write block-level RTL and support full-chip integration of high-speed IPs such as ODSP, D2D IP, SerDes XSR, SerDes PAM4 integrated drivers/TIA, and control functions. You will work closely with verification teams to ensure complete functional closure, with physical design teams to support implementation readiness, and with post-silicon teams to help drive successful product bring-up and release to production.

Who You Are
  • Bachelor’s degree in Electrical Engineering or related field; Master’s degree preferred.
  • Strong technical leader with 6-8 years of hands-on experience in digital design, RTL development, and ASIC/SoC integration.
  • Strong understanding of digital architecture, finite state machines, control logic, datapath design, and interface design.
  • Familiarity with protocols such as SPI, I2C, APB, AXI, or similar interfaces.
  • Experience supporting block-to-chip integration.
  • Strong knowledge of ASIC/SoC design flow, including RTL development, simulation, lint, CDC/RDC, synthesis, formal/equivalence checking, DFT, and implementation handoff.
  • Experience with low-power design methodologies such as UPF/CPF.
  • FPGA experience is a plus.
  • Experience supporting lab bring-up, post-silicon validation, or ATE enablement is a plus.
  • Strong analytical, problem-solving, teamwork and debugging skills.
 Minimum Qualifications)·        Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or a related field.·        3+ years of digital design or ASIC/SoC RTL design experience, with demonstrated technical leadership in block or subsystem development.·        Strong skills in RTL design, digital integration, ASIC design flow, and DFT.·        Proficiency in Verilog/SystemVerilog.

 Why Cisco

WE ARE CISCO

#WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference. Here’s how we do it.

We embrace digital and help our customers implement change in their digital businesses. Some may think we’re “old” (30 years strong!) and only about hardware, but we’re also a software company. And a security company. A blockchain company. An AI/Machine Learning company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do – you can’t put us in a box!

But “Digital Transformation” is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it.)

Day to day, we focus on the give and take. We give our best, we give our egos a break and we give of ourselves (because giving back is built into our DNA.) We take accountability, we take bold steps, and we take difference to heart. Because without diversity of thought and a commitment to equality for all, there is no moving forward.

So, you have colorful hair? Don’t care. Tattoos? Show off your ink. Like polka dots? That’s cool.


Why Cisco? 

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. 

We are Cisco, and our power starts with you. 


Disclaimer

To ensure that we hire the best talent in the right way, we follow a strict hiring process and recently, Cisco has been made aware of fraudulent recruiters claiming to be from the company. Please be advised that any communication from Cisco about careers will:

  • be in direct response to an application you have submitted through the company career site
  • begin with screening or an interview
  • originate from a Cisco email address, and
  • be conducted across email, phone, or WebEx

Cisco will never make a job offer without conducting an interview process or ask you for money in any way. If you have been requested to apply for a role or have received an offer from a site other than https://careers.cisco.com or cisco.wd5.myworkday.com, do not provide any personal identifying information, including your Aadhaar or other personal identifying number, birth certificate, banking information, driver's license, or passport.

If you are the target of a recruiting scam, consider filing a report with your local law enforcement authorities. Cisco bears no responsibility, and cannot be held liable, for any claims, damages, expenses, or other inconvenience resulting from or in any way connected to recruiting scams.


Skills Required

  • Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field
  • 3+ years of digital design or ASIC/SoC RTL design experience
  • Demonstrated technical leadership in block or subsystem development
  • Strong skills in RTL design, digital integration, ASIC design flow, and DFT
  • Proficiency in Verilog/SystemVerilog
  • 6-8 years of hands-on experience in digital design, RTL development, and ASIC/SoC integration
  • Understanding of digital architecture, finite state machines, control logic, datapath design, and interface design
  • Familiarity with SPI, I2C, APB, AXI, or similar interfaces
  • Experience supporting block-to-chip integration
  • Knowledge of ASIC/SoC design flow, including simulation, lint, CDC/RDC, synthesis, formal/equivalence checking, DFT, and implementation handoff
  • Experience with low-power design methodologies such as UPF/CPF
  • FPGA experience
  • Experience supporting lab bring-up, post-silicon validation, or ATE enablement

Cisco Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cisco and has not been reviewed or approved by Cisco.

  • Healthcare Strength — Health coverage is described as broad, with medical options including PPOs, high-deductible plans, and regional HMOs. Feedback suggests robust wellness and mental-health resources, with some locations offering on-site support and second medical opinions.
  • Leave & Time Off Breadth — Time off is highlighted through paid holidays, paid time off, and additional recharge days such as “Days for Me,” with generous volunteer time also mentioned. Feedback suggests these programs help support rest, volunteering, and critical life events.
  • Parental & Family Support — Parental and family support appears extensive, including paid child-bonding leave, family medical leave, and caregiving resources. Observations also point to family-planning assistance and adoption or surrogacy support in some regions.

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The Company
HQ: San Jose, CA
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Year Founded: 1984

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Cisco (NASDAQ: CSCO) enables people to make powerful connections--whether in business, education, philanthropy, or creativity. Cisco hardware, software, and service offerings are used to create the Internet solutions that make networks possible--providing easy access to information anywhere, at any time. Cisco was founded in 1984 by a small group of computer scientists from Stanford University. Since the company's inception, Cisco engineers have been leaders in the development of Internet Protocol (IP)-based networking technologies. Today, with more than 71,000 employees worldwide, this tradition of innovation continues with industry-leading products and solutions in the company's core development areas of routing and switching, as well as in advanced technologies such as home networking, IP telephony, optical networking, security, storage area networking, and wireless technology. In addition to its products, Cisco provides a broad range of service offerings, including technical support and advanced services. Cisco sells its products and services, both directly through its own sales force as well as through its channel partners, to large enterprises, commercial businesses, service providers, and consumers.

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