The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With ~2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.
You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in Bangalore India with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities.
Your Impact
- Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
- Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
- Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
- Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
- The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.
Minimum Qualifications:
- Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 12 years of experience.
- Knowledge of the latest innovative trends in DFT, test and silicon engineering.
- Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
- Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
- Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design
- Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
- Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
- Experience working with Gate level simulation, debugging with VCS and other simulators.
- Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687
- Strong verbal skills and ability to thrive in a multifaceted environment
- Scripting skills: Tcl, Python/Perl.
Preferred Qualifications:
- Verilog design experience - developing custom DFT logic & IP integration; familiarity with functional verification
- DFT CAD development - Test Architecture, Methodology and Infrastructure
- Test Static Timing Analysis
- Post silicon validation using DFT patterns.
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
Skills Required
- Bachelor's or Master's Degree in Electrical or Computer Engineering with at least 12 years of experience
- Knowledge of DFT, test and silicon engineering trends
- Experience with JTAG protocols, Scan and BIST architectures, including memory BIST and boundary scan
- Experience with ATPG and EDA tools (TestMax, Tetramax, Tessent tool sets, PrimeTime)
- Verification skills including SystemVerilog logic equivalency checking and test-timing validation
- Experience with gate-level simulation and debugging using VCS and other simulators
- Post-silicon validation and debug experience; ability to work with ATE patterns and P1687
- Scripting skills: Tcl and Python or Perl
- Ability to craft solutions and debug with minimal mentorship; strong verbal communication
- Verilog design experience for custom DFT logic and IP integration
- DFT CAD development experience (Test Architecture, Methodology, Infrastructure)
- Test Static Timing Analysis
- Post-silicon validation using DFT patterns
Cisco Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cisco and has not been reviewed or approved by Cisco.
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Healthcare Strength — Health coverage is described as robust with multiple plan options and access to onsite/virtual LifeConnections Health Centers on major campuses. Company materials also highlight mental-health resources and comprehensive preventive care, supporting strong core medical benefits.
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Leave & Time Off Breadth — Time away includes company‑wide recharge days, a paid birthday, a year‑end shutdown, and paid Critical Time Off for emergencies. Paid volunteer days further expand opportunities to step away and recharge.
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Parental & Family Support — Policies include a global minimum for paid parental leave for primary caregivers, caregiving concierge services, and on‑site children’s learning centers in select locations. In the U.S., family‑building support is consolidated under Carrot with a defined lifetime maximum, indicating structured assistance across fertility, preservation, adoption, and surrogacy.
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What We Do
Cisco (NASDAQ: CSCO) enables people to make powerful connections--whether in business, education, philanthropy, or creativity. Cisco hardware, software, and service offerings are used to create the Internet solutions that make networks possible--providing easy access to information anywhere, at any time. Cisco was founded in 1984 by a small group of computer scientists from Stanford University. Since the company's inception, Cisco engineers have been leaders in the development of Internet Protocol (IP)-based networking technologies. Today, with more than 71,000 employees worldwide, this tradition of innovation continues with industry-leading products and solutions in the company's core development areas of routing and switching, as well as in advanced technologies such as home networking, IP telephony, optical networking, security, storage area networking, and wireless technology. In addition to its products, Cisco provides a broad range of service offerings, including technical support and advanced services. Cisco sells its products and services, both directly through its own sales force as well as through its channel partners, to large enterprises, commercial businesses, service providers, and consumers.
