Analog and Mixed Signal IP Architect

Job Details:

Job Description: 

Do Something Wonderful!

Intel put Silicon in Silicon Valley. No one else is obsessed with engineering and have a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

Who We Are

This team is responsible for defining next-generation die-2-die (D2D) interconnect solutions for Intel SOCs.  Work includes interfacing with customers to gather requirements, exploring and defining cutting edge IO PHY solutions with industry-leading power efficiency and bandwidth density, worthing hand in hand with implementation team all the way to IP and product qualification.

Who You Are

Responsibilities include but are not limited to:

• Develops and drives analog and mixed signal IP architectures, signal processing algorithms, and calibration algorithms for SoC independent analog mixed signal (AMS) IPs.

• Performs topdown architectural analysis of AMS systems and conducts transistor level feasibility study for various AMS circuits.

• Drives analog and mixed signal functionality, connectivity, and configuration.

• Enhances system performance using digitally assisted analog techniques and optimum partitioning of analog and digital circuits.

• Evaluates feasibility tradeoffs, explores, and defines new approaches and novel architectures for analog and mixed signal IP.

• Invents, conceptualizes, and specifies microarchitecture and architectural features for next generation to deliver optimized analog and mixed signal IP for multiple segments from high performance computing to extreme low power products.

• Develops modeling scenarios and modeling for new architectures/features for analog and mixed signal IPs.

• Performs modeling simulations, estimation, and optimization for power and area and conducts analysis of test results using advanced statistics and data predictions for benchmarking and determining areas for improvement.

• Provides experimental/proof of concept changes for proposing design alternatives meeting performance, power, area, and timing constraints.

• Reviews, challenges, and influences cross functional roadmaps and defines technology targets for future analog and mixed signal IPs. Collaborates with IP design engineers and IP verification engineers to design and validate SoC independent IPs.

• Supports SoC architects, SoC design engineers, and SoC verification engineers in selecting, configuring, integrating, and validating SoCs that utilize analog and mixed signal IPs.

• Expected to perform well in a fast-paced collaborative team environment, to execute to meet our customer commitment on time and with high quality; and at the same time, to explore new innovative ideas that can improve and optimize the design.

Qualifications:

You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
 

Minimum Qualifications

• The candidate must have Bachelor’s Degree in Computer Engineering/Computer Science with 6+ years’ of experience -OR- Master’s Degree in Computer Engineering/Computer Science with 4+ years’ of experience in analog design and development -OR- PhD in Computer Engineering/Computer Science plus 2+ years of experience in analog design and development

• Experience in designing analog and mixed-signal circuits in standard CMOS technologies such as op-amps, comparators, bandgap references, linear regulators etc

• Experience with backend performance and reliability verification tools including Monte Carlo, EMIR, static/dynamic MOSFET voltage checks, etc

• Knowledge and understanding of switching voltage regulators such as Buck converters is a plus.

• Post-Si debug experience and experience of productizing design in high volume production is a plus.

Job Type:Experienced Hire

Shift:Shift 1 (United States of America)

Primary Location: US, California, Santa Clara

Additional Locations:US, Oregon, Hillsboro

Business group:IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

Annual Salary Range for jobs which could be performed in the US:

$186,070.00-$262,680.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.