Jobs at Velaura AI, Inc.

Own the power architecture for Physical AI SoCs from early design through tape-out and production. Define power domains, DVFS, power states, power delivery, low-power techniques, PMIC interfaces, control systems, telemetry, and firmware policies. Establish power and thermal budgets, model PPA trade-offs, implement UPF-based methodology, and validate power management through silicon bring-up. Collaborate across silicon, firmware, thermal, package, and platform software teams while mentoring engineers and setting organizational standards.

Leads the architecture and delivery of a customer-facing SDK for an edge AI SoC. Owns APIs, command-line tools, samples, documentation, developer workflows, packaging, compatibility, release readiness, and developer portal requirements. Partners across AI, multimedia, robotics, kernel, tools, and SQA teams to support board bring-up, model deployment, camera pipelines, ROS examples, and production workloads. Hires, mentors, and leads engineers focused on SDKs, developer tools, documentation, portals, and sample applications.

Own the end-to-end security architecture for Physical AI SoCs, including hardware roots of trust, secure boot, key management, trusted execution, cryptographic acceleration, secure updates, attestation, and device identity. Lead threat modeling against physical, side-channel, fault-injection, and supply-chain attacks. Partner across silicon, firmware, safety, and platform teams from architecture through production, establish security standards, mentor engineers, and support certification and customer assurance.

Own the end-to-end security architecture for Physical AI SoCs, including root of trust, secure boot, key management, secure debug, trusted execution, cryptographic acceleration, model protection, and secure updates. Lead threat modeling against physical and cyber attacks, translate risks into hardware and firmware requirements, and partner across silicon, firmware, safety, and software teams through production. Establish security standards, support certification and audits, and mentor engineers.

Designs and evaluates AI model architectures for efficient hardware implementation. Analyzes transformers, training and inference pipelines, computation graphs, dataflows, and performance models. Collaborates with software and hardware architects to optimize models, algorithms, and specialized compute platforms. The role also explores emerging architectures and applications in robotics, autonomous systems, and embodied AI.

Own front-end CAD automation for RTL design, verification, DFT handoff, emulation, and FPGA prototyping. Build and maintain lint, CDC, formal, simulation, regression, coverage, register-generation, and AI-assisted workflows. Manage tool versions, compute infrastructure, flow health, and issue resolution while improving engineering productivity and partnering with design, verification, DFT, and physical design teams.

Own the functional safety architecture and lifecycle for Velaura’s Physical AI SoCs, from architecture through production. Lead hazard, failure, and fault analyses; define safety mechanisms and quantitative metrics; embed safety requirements across RTL, firmware, and platform software; and build the safety case for certification. Establish processes, coordinate with assessors and customers, mentor engineers, and align functional safety with cybersecurity, reliability, and SOTIF.

Design and verify Velaura’s Physical AI SoC from RTL blocks through complete hardware and software systems. Responsibilities include building SoC simulation environments, verifying boot, security, clock/reset, low-power, IO and memory subsystems, running CDC/RDC analysis, evaluating latency, bandwidth and QoS, and supporting coverage closure, sign-off and tape-out. The role requires extensive SoC verification experience with SystemVerilog, UVM, C/C++, CPU-based platforms, PCIe, LPDDR, UPF and low-power verification flows.

Design and optimize RTL for Velaura’s Physical AI SoC, collaborating with architects, software, verification, and physical design teams. Responsibilities include developing microarchitectures, compute engines, memory subsystems, interconnects, DMA engines, control processors, and power-management logic. The role involves hardware/software co-design, performance optimization, and tradeoffs across power, performance, area, scalability, and reliability.

Design and own SoC power-management RTL, including digital power meters, activity monitors, throttlers, thermal and current control loops, clock/reset architecture, DVFS, power domains, retention, and telemetry. Collaborate with architecture, physical design, package, firmware, software, verification, and physical design teams to manage voltage droop, thermal limits, power delivery, and adaptive clocking. Correlate power estimates from RTL through silicon and support production SoC development.

Lead RTL development for a next-generation Physical AI SoC, translating architectural requirements into production-quality microarchitectures. Responsibilities include hardware/software co-design, compute and memory subsystem design, power-performance-area optimization, architecture and RTL reviews, silicon bring-up, engineering process development, and mentoring RTL engineers. The role collaborates extensively with architects, verification, physical design, performance modeling, and software teams.

Own functional verification of custom CPU units from test planning through coverage closure. Build SystemVerilog and UVM environments with C/C++, stimulus, checkers, assertions, trackers, and coverage. Verify instruction execution, caches, memory ordering, coherence, exceptions, privilege behavior, and performance. Execute regressions, support emulation and FPGA prototyping, enable pre-silicon software bring-up, and debug hardware-software issues across multidisciplinary teams.

Develop and execute verification strategies for complex SoC hardware, including compute engines, memory systems, interconnects, processors, DMA, and system software interactions. Build SystemVerilog and UVM environments, assertions, checkers, scoreboards, and formal verification workflows. Analyze performance, latency, bandwidth, QoS, and real-time behavior; support emulation, FPGA prototyping, pre-silicon bring-up, post-silicon debugging, and hardware-software root-cause analysis.

Develop and execute verification strategies for complex Physical AI SoC components and full HW/SW systems. Build SystemVerilog and UVM environments, assertions, checkers, scoreboards, and formal verification flows. Verify processors, memory, interconnects, DMA engines, and accelerators for correctness, performance, safety, and reliability. Lead emulation, FPGA prototyping, pre-silicon validation, post-silicon debugging, root-cause analysis, and system-level workload testing while collaborating across architecture, RTL, software, and systems teams.

Own verification of custom AI accelerator hardware, including matrix and vector compute engines. Develop SystemVerilog and UVM environments, reference models, assertions, checkers, coverage, and regression infrastructure. Verify numerical precision, quantization, data flow, performance, and reliability across RTL blocks and subsystems. Collaborate with architecture, RTL, software, compiler, and runtime teams through emulation and silicon bring-up.

Own formal verification for complex SoC blocks, including CPUs, floating-point units, vector engines, and datapaths. Develop SVA properties, formal testbenches, equivalence checks, abstractions, constraints, and reusable formal applications. Debug counterexamples, close coverage, verify IEEE-754 arithmetic, maintain automation and CI infrastructure, and collaborate with architecture, RTL, and simulation teams on verification signoff.

Design and optimize RTL for a high-speed, low-power SoC memory subsystem. Responsibilities include memory controller and PHY integration, DFI interfaces, initialization and training, calibration, timing closure, power management, performance optimization, ECC and error reporting. The role collaborates with architecture, software, verification, physical design, and memory IP teams through silicon bring-up, while contributing to microarchitecture, scheduling, QoS, reliability, and AI-assisted engineering workflows.

Own RTL design and optimization for key portions of a Physical AI SoC through tapeout. Develop microarchitectures, compute engines, memory subsystems, interconnects, DMA engines, and power-management logic. Collaborate with architecture, software, verification, and physical design teams to optimize performance, power, area, scalability, and reliability. Lead design reviews, analyze bottlenecks, drive hardware/software co-design, and mentor junior engineers.

Own the architecture and technical direction of a heterogeneous AI SoC runtime spanning sensor ingest, preprocessing, inference, postprocessing, and application delivery. Define execution, memory, synchronization, driver, firmware, compiler-runtime, observability, resilience, and validation architectures. Lead cross-functional engineers while contributing hands-on to production systems software, performance optimization, APIs, and low-level interfaces for robotics and edge AI workloads.

Own verification of custom AI accelerator hardware, including matrix and vector engines. Develop SystemVerilog and UVM environments, reference models, assertions, checkers, coverage, and regressions. Verify numerical precision, quantization, data flow, performance, latency, and power efficiency across RTL blocks and complete systems. Collaborate with architecture, software, compiler, runtime, and systems teams through design bring-up, emulation, and pre-silicon validation.