Teams at Velaura AI, Inc.

Own the power architecture for Physical AI SoCs from early design through tape-out and production. Define power domains, DVFS, power states, power delivery, low-power techniques, PMIC interfaces, control systems, telemetry, and firmware policies. Establish power and thermal budgets, model PPA trade-offs, implement UPF-based methodology, and validate power management through silicon bring-up. Collaborate across silicon, firmware, thermal, package, and platform software teams while mentoring engineers and setting organizational standards.

Leads the architecture and delivery of a customer-facing SDK for an edge AI SoC. Owns APIs, command-line tools, samples, documentation, developer workflows, packaging, compatibility, release readiness, and developer portal requirements. Partners across AI, multimedia, robotics, kernel, tools, and SQA teams to support board bring-up, model deployment, camera pipelines, ROS examples, and production workloads. Hires, mentors, and leads engineers focused on SDKs, developer tools, documentation, portals, and sample applications.

Own the end-to-end security architecture for Physical AI SoCs, including hardware roots of trust, secure boot, key management, trusted execution, cryptographic acceleration, secure updates, attestation, and device identity. Lead threat modeling against physical, side-channel, fault-injection, and supply-chain attacks. Partner across silicon, firmware, safety, and platform teams from architecture through production, establish security standards, mentor engineers, and support certification and customer assurance.