Jobs at Solidigm

Develops and validates mechanical simulations for advanced storage and memory products. Performs structural and thermal-mechanical analysis, including finite element modeling, solder joint reliability, temperature cycling fatigue, product disassembly, and PCB strain evaluation. Improves simulation methodologies, develops experimental test models, identifies design risks, and collaborates with design, manufacturing, quality, and engineering teams to optimize product performance, reliability, and manufacturability.

Undergraduate interns support hardware design, evaluation, debugging, board bring-up, hardware and firmware analysis, product development, test-data analysis, scripting, documentation, and cross-functional engineering work for data center SSD products.

Undergraduate interns will develop and test software tools, backend systems, firmware features, automation, and engineering workflows for data center SSD products. Responsibilities include coding in Python or C/C++, Linux-based development, debugging software and firmware, analyzing engineering data, collaborating with cross-functional teams, and documenting technical work. Assignments may involve embedded software, device drivers, storage technologies, APIs, AI-assisted programming, or applied data analysis.

Graduate interns will design, develop, test, and debug software, firmware, embedded systems, validation tools, and AI-enabled engineering workflows. Responsibilities include automation, regression testing, log and performance analysis, root-cause investigation, and collaboration with firmware, software, validation, and hardware teams supporting SSD and storage products.

Supports NAND semiconductor high-volume manufacturing through product disposition, yield monitoring, failure analysis, sample management, and maintenance of laboratory analysis tools. The role troubleshoots and maintains hardware and software, supports electrical failure analysis, manages quality samples, and collaborates with product engineering, test, manufacturing, quality, and reliability teams to resolve production issues and drive operational improvements.

Lead firmware architecture for next-generation SSD products, driving cross-domain technical decisions, customer feature requirements, and product-level initiatives. Develop and review C/C++ firmware, low-level system architectures, and device features; perform testing, debugging, benchmarking, and failure analysis. Collaborate with ASIC, hardware, validation, manufacturing, product engineering, and customers to translate requirements into development plans, guide technology roadmaps, establish engineering standards, and mentor technical teams within an Agile/Kanban environment.

Leads technical revenue accounting under ASC 606 and IFRS 15, evaluates complex contracts, strengthens revenue processes and controls, supports financial close and audits, and partners with cross-functional teams on ERP, CRM, and revenue systems. Advises stakeholders, monitors accounting guidance, develops policies and training, drives process improvements, and mentors revenue accounting staff.

Lead global revenue accounting under U.S. GAAP and IFRS, including complex contract assessments, ASC 606 and IFRS 15 memoranda, revenue reserves, controls, audits, and financial close support. Partner with Sales, Legal, Supply Chain, IT, and other teams on contract structures, order-to-cash processes, ERP/CRM integrations, and automation. Monitor accounting guidance, maintain policies and training, improve scalable processes, and mentor revenue accounting staff.

Lead 3D NAND process integration and next-generation semiconductor technology qualification. Define process flows and specifications, resolve process-related issues using model-based analysis, and apply statistical tools to improve performance, reliability, and yield. Coordinate multidisciplinary engineering teams through product qualification and manufacturing transfer, troubleshoot semiconductor processes, drive continuous improvement, and transfer new technologies into high-volume production.

Performs pre-silicon verification of advanced 3D NAND designs. Responsibilities include creating verification plans, developing UVM-based directed and constrained-random tests, debugging simulations, defining functional coverage, maintaining SystemVerilog assertions, building mixed-signal models and full-chip verification environments, and automating regressions, workflow execution, results processing, and data collection.

Develops and deploys NAND Flash component test specifications, methodologies, and flows for high-volume manufacturing. Leads product qualification, NPI and sustaining yield improvement, analyzes manufacturing and test data, and troubleshoots failures with design, process, reliability, and test engineering teams. Responsibilities include validating test code, reviewing checkout data, supporting tape release, communicating yield and test-coverage roadmaps, and optimizing test coverage, efficiency, and cycle time.

Lead architecture for next-generation enterprise SSDs, defining domain-level vision, system specifications, hardware/software partitioning, and performance strategies. Drive trade-offs across performance, power, cost, scalability, and schedule throughout product development, validation, and bring-up. Influence ASIC and firmware design, partner with cross-functional engineering teams, incorporate emerging technologies, communicate with technical and executive stakeholders, and mentor engineers and architects.

Lead domain-level architecture for next-generation data center SSDs, defining architectural vision, system specifications, hardware/software partitioning, and performance strategies. Drive trade-offs across performance, power, cost, scalability, and schedule throughout the product lifecycle. Influence ASIC, firmware, hardware, controller, and validation teams, guide technical execution, incorporate emerging technologies, and mentor engineers and architects.

Lead architecture for next-generation data center SSDs, defining domain architectures, system specifications, hardware/software partitioning, and performance strategies. Drive end-to-end product design from concept through validation and bring-up, influence ASIC and firmware decisions, resolve technical trade-offs, guide cross-functional engineering teams, incorporate emerging technologies, and mentor engineers and architects.

Leads the global risk and controls function, including SOX 404 compliance, internal control design, management testing, remediation, risk governance, and control automation. Partners with Finance, IT, Legal, Internal Audit, and operations to standardize processes, strengthen ERP controls, support SEC reporting requirements, and maintain an audit-ready environment. Builds and manages the Risk & Controls organization while advising executive leadership on control deficiencies, compliance status, and operational improvements.

Designs and executes NAND cell and array characterization experiments focused on performance, reliability, power, and endurance. Develops trims to reduce program/read disturb and optimize operating parameters. Applies NAND device physics, statistical analysis, and programming to identify failure mechanisms, analyze trade-offs, and implement solutions. Collaborates with device, design, reliability, and product/test engineering teams to improve NAND product quality and performance.

Designs and executes NAND cell and array characterization experiments, develops trims for improved read performance and reliability, analyzes semiconductor data, builds predictive models, and collaborates with device, design, reliability, test, and wafer fabrication teams. The role drives wafer-level reliability experiments, production trim releases, degradation scorecards, screening improvements, and back-end test yield optimization for next-generation 3D NAND products.

Architect, design, verify, and sign off logic and circuit blocks for 3D NAND flash memory. Responsibilities include SystemVerilog RTL development, synthesis, timing analysis, ECOs, microcode algorithm optimization, verification, AMS and post-silicon analysis, DFT development, power and performance modeling, and debug across pre- and post-silicon cycles.

Debug internal validation and customer SSD failures across varied architectures and failure modes. Collaborate with firmware, hardware, platform, validation, operating system, and driver teams to determine root causes of performance, reliability, and functional issues. Analyze telemetry, use PCIe/NVMe protocol analyzers and firmware debuggers, perform system-level debugging, develop scripts, and share failure-analysis methodologies with junior engineers.

Develop predictive TCAD models and computational tools for 3D NAND cell arrays and CMOS technology development. Build simulation methods across NAND technology nodes, collaborate with process and integration teams, design and validate experiments, and analyze E-test data against inline parameters. Present modeling insights and solutions to address scaling constraints. The role requires strong semiconductor and NAND device physics expertise, computational geometry skills, Synopsys simulator proficiency, and cross-functional collaboration.