Teams at Silvaco Inc

Develops, validates, and maintains SRAM, ROM, and register-file memory views and models, including Liberty timing/power models and behavioral Verilog/SystemVerilog models. Builds verification regressions, Tessent MBIST descriptions, TetraMAX ATPG patterns, and FastScan flows. Automates model-generation and QA processes using Perl, Python, TCL, and Shell on Unix/Linux. Collaborates with design, DFT, physical design, and STA teams, supports silicon validation, documents deliverables, and mentors junior engineers.

Leads the memory layout team and owns resource planning, development, recruiting, methodology, and technical quality. Remains hands-on in floorplanning, placement, routing, physical verification, parasitic extraction, EMIR, reliability closure, and tape-out of SRAM, ROM, DPRAM, register file, and related memory IP. Develops automation scripts and layout standards, drives process-node porting, resolves signoff issues, and collaborates with design, CAD, foundry, and global stakeholders.

Owns custom layout design and physical verification for critical memory IP, including floorplanning, placement, routing, extraction, EMIR analysis, ECO implementation, and signoff. Develops automation scripts, improves layout methodologies, supports silicon validation, and mentors junior engineers. Collaborates with memory design, modeling, DFT, physical design, CAD, and process teams to deliver complete memory instances or compiler sub-families.