Jobs at Samsung Semiconductor, Inc.

Lead verification for AI accelerator IP blocks, developing UVM-based testbenches, automation, simulations, regressions, test plans, and quality metrics. Collaborate with architects, RTL, compiler, and simulation engineers to debug failures and validate functionality and performance across IP, die, SoC, and system levels. Document verification strategies, improve test environments, and mentor junior engineers.

Build a cost-model-guided auto-tuning framework for PyTorch and Triton kernels on a compute-near-memory AI accelerator. Responsibilities include designing search spaces, legality rules, cost models, benchmarking harnesses, tuning caches, and integrations with torch.compile, Inductor, and Triton. The intern will measure LLM inference performance, support data-placement-aware tuning, collaborate with compiler and open-source teams, and deliver tested, documented code and results.

Build AgentSysBench benchmarks and profiling tools for AI agent frameworks and LLM serving workloads. Develop runtime adapters, workload benchmarks, and trace replay systems; profile CPU, memory, GPU, and accelerator performance; measure DDR5, HBM, and CXL bandwidth and latency; evaluate KV-cache sharing and memory expansion; develop memory tiering cost models; and present findings to the team.

Develop, debug, optimize, and validate firmware for enterprise SSD products on complex embedded multi-core architectures. Collaborate with a mentor on firmware upgrade mechanisms, resolve firmware issues, support customer qualification, and contribute to advanced SSD storage research. Participate in scrum meetings and complete assigned development tasks. Gain experience with NVMe, PCIe, OCP, SSD firmware architecture, boot processes, bring-up code, and binary management systems.

Design and optimize ML compilers for high-performance deep learning applications across diverse hardware platforms. Develop staged lowering infrastructure, optimize data locality and compiler execution, integrate ML techniques with hardware architectures, debug compiler issues, support customers, and contribute to documentation. Collaborate with hardware architects, software developers, and cross-functional teams while researching emerging AI/ML computing technologies.

Develops and executes DRAM product marketing strategy by analyzing market demand, pricing, competition, customer trends, and total addressable market. Informs supply allocation and production plans, equips Sales with customer and competitive insights, creates presentations, represents Samsung in customer meetings, and collaborates with technical, sales, and headquarters teams. The role is based onsite in San Jose and focuses on enterprise OEM and datacenter markets.

Develop next-generation DRAM architecture, floor plans, row and column bank circuits, datapaths, test modes, and power delivery optimization. Identify device requirements, analyze silicon electrical data, validate core architecture performance, and collaborate with process integration, device modeling, quality assurance, product engineering, and customers. Document design specifications, performance analyses, and test plans while contributing to Samsung’s memory technology leadership.

Leads architecture, design, and implementation of ML compilers for deep learning applications on next-generation AI hardware. Develops lowering infrastructure, optimization algorithms, memory scheduling, kernel fusion, and code generation. Partners with hardware, runtime, ML framework, and research teams on co-design, troubleshoots complex compiler issues, mentors engineers, and establishes technical standards and documentation.

Design memory unit cell arrays, core layouts, control logic layouts, test structures, and parametric cells for next-generation memory technology. Collaborate on process integration, design architecture, and technology co-optimization. Customize DRCs, support tapeout database integration, document designs, and interact with customers. The role is onsite in San Jose five days weekly with approximately 10% travel.

The Compensation Partner manages market benchmarking, pay competitiveness analysis, job evaluation, and annual compensation processes, including salary reviews, bonuses, incentives, and promotions. The role develops data models, dashboards, governance tools, and executive reports; advises HR and business leaders; supports compensation policy design, communication, and training; and partners on HRIS configuration and testing to ensure effective, scalable compensation workflows.

Leads DRAM product planning, customer design-in, technical qualification, and mass-production transitions. The role aligns customer hardware roadmaps with Samsung memory technology, defines specifications and customized interfaces, resolves system-level engineering issues, develops value-based commercial models, and coordinates Sales, Marketing, R&D, Quality, and customers. Responsibilities include managing risks, milestones, strategic partnerships, TCO optimization, and next-generation custom HBM and logic base-die development.

Deploy and benchmark LLM inference on NVIDIA GPU systems, configure KV cache offloading to network-attached storage, analyze performance bottlenecks with Python, and collaborate with FPGA, SoC, and firmware engineers to validate end-to-end data paths. The intern will quantify storage requirements, maintain reproducible experiments, and present findings that inform future SSD controller architectures.

Develop next-generation DRAM semiconductor technology through process integration, wafer fabrication planning, design-rule definition, device component integration, and process module development. Analyze inspection and measurement data to improve performance and reliability, identify technology gaps, and coordinate with simulation, process development, architecture, circuit design, and quality teams. The role also involves customer interactions and technical leadership across cross-functional teams.

Manage HBM sales for a strategic AI infrastructure account, leading account strategy, pricing, supply allocation, product transitions, qualification timelines, and long-term agreements. Build customer relationships, analyze market and demand data, support AI accelerator and datacenter programs, and coordinate engineering, product, operations, quality, and executive teams to deliver customer commitments and resolve issues.

Supports development, simulation, and optimization of SRAM circuits. Responsibilities include transistor-level schematic design for bitcells, sense amplifiers, and peripheral circuits; functional, timing, power, and reliability simulations; technical documentation; and research into advanced SRAM architectures. The intern will use EDA tools and scripting languages while contributing to architecture, design, and silicon-level verification.

Develop systems software for memory and storage pools supporting reinforcement-learning post-training of large language models. Profile resource bottlenecks, implement bounded memory staging and asynchronous storage features, integrate with RL frameworks, preserve checkpoint consistency, measure performance across pooled configurations, and deliver tested, documented code suitable for review and open-source contribution. The role is onsite in San Jose and reports to a Principal Engineer.

Lead end-to-end SRAM circuit design for advanced semiconductor nodes, including memory arrays, bit cells, sense amplifiers, decoders, control circuits, custom layouts, and verification. Optimize power, performance, area, and yield using circuit simulation and variation analysis. Develop automation methodologies, support test planning and silicon bring-up, perform debug, mentor engineers, and contribute to patents and technical publications.

Develop and validate IP-level power macromodels for AI memory components. Extract power features from RTL, SystemC, and C simulations; calibrate models using synthesis, circuit references, and measured data; validate against RTL, gate-level analysis, and silicon; and integrate models into trace-driven simulation flows. The role is onsite in San Jose and includes collaboration with hardware, software, and thermal experts.

Leads the HR Business Partner function supporting R&D, Sales, and Support organizations. Oversees HRBP staff, partners with executive leadership, aligns people strategies with business goals, and drives talent management, succession planning, leadership development, workforce planning, performance management, rewards, organizational assessments, and change initiatives. Coordinates with HR Centers of Excellence and headquarters while providing strategic and tactical guidance across the organization.

Leads Samsung Semiconductor’s sales engagement with a strategic Tier 1 customer. Responsibilities include account strategy, customer relationship management, design-win development for DRAM and NAND products, sales forecasting, revenue attainment, negotiations, product and roadmap support, competitive analysis, cross-functional collaboration, international customer meetings, and leadership of a high-performing sales team.