Assist management with scheduling, secretarial tasks, and information management to support decision making and work performance. Requires at least 5 years of experience.

Design and simulate high-speed I/O analog-mixed circuits, guide layout optimization, and ensure specifications for performance and functionality.

Lead design and validation of LiDAR sensors and precision optics, performing ray-tracing simulations and experimental validations.

Develop and optimize memory centric computing systems; troubleshoot hardware issues, collaborate with engineers, and stay updated on AI/ML advancements.

Lead end-to-end SRAM memory circuit design for advanced nodes, optimizing performance, power, area, and yield. Perform circuit simulation, custom layout, physical verification, automation scripting, silicon bring-up support, mentor junior engineers, and contribute to SRAM methodology and publications.

The Chief of Staff will shape and execute U.S. memory-sales strategy, oversee sales processes, lead initiatives, and represent sales leadership in key engagements.

The role involves developing Generative and Agentic AI solutions, designing ML models, optimizing large-scale ML models, and collaborating with cross-functional teams.

Lead architecture and circuits for high-speed interconnect transceiver designs. Supervise designers and support silicon validation. Utilize low-power, low-voltage analog components.

The Senior Manager, Technical Marketing focuses on custom SoC business development, technical requirements review, customer engagement, and cross-functional collaboration with internal teams for strategic solutions. They build customer relationships and manage account activities, requiring a blend of technical expertise and business acumen.

Lead SoC-level microarchitecture, top integration, logic design and RTL implementation for memory/storage controllers. Integrate and review 3rd-party IPs (UCIe, DDR, CPU, Ethernet), collaborate with verification and physical design teams on synthesis, timing, DFT, CDC, lint, and silicon bring-up to deliver production-ready silicon.

The Sales Specialist manages orders, verifies pricing, coordinates logistics, and handles customer inquiries while ensuring efficient order fulfillment and account management.

The role involves developing and validating CMOS Image Sensor technologies, establishing image quality standards, and conducting performance analysis. The engineer will work closely with cross-functional teams to improve system performance and automate testing procedures.

The SoC Architect leads the design of SoC architectures to meet PPA targets, collaborates across teams, and resolves technical risks.

Develop software infrastructure and protocol stack for WLAN chipsets, focusing on firmware development for 802.11 MAC layer, collaborating on feature deliverables and ensuring production quality.

Lead the strategic development of custom silicon solutions for datacenter clients, ensuring specifications meet unique workload needs while coordinating cross-functional teams to maintain project timelines.

The role involves analog design engineering with a focus on high-speed I/O design, circuit feasibility studies, and layout supervision, emphasizing communication and teamwork.

Lead strategic direction and execution of the sales technology stack (primarily Salesforce), driving automation, integrations, data quality, reporting, enablement programs, training, and collaboration with IT to boost sales productivity and resolve system issues.

Lead Samsung foundry customer programs across process technologies, serving as primary technical account interface. Drive business growth, coordinate NPI to production with internal teams, ensure customer satisfaction, and achieve manufacturing milestones.

The Senior Executive Assistant supports the VP of Memory Sales by managing the calendar, overseeing three remote offices, organizing meetings, and enhancing office operations. Responsibilities include budget tracking, communication facilitation, and vendor liaison.

Lead the development of SRAM layout and verification, collaborate with designers, optimize layouts for performance, and mentor junior engineers.