Jobs at Samsung Semiconductor, Inc.

Serve as a strategic Learning and Development advisor to senior leaders, diagnosing capability gaps and designing customized enablement solutions. Build and deliver curricula, workshops, e-learning, toolkits, and AI-enabled learning experiences for Sales, Marketing, and Staff organizations. Facilitate programs, manage vendors and SMEs, promote adoption, measure outcomes, and continuously improve solutions using stakeholder feedback and data.

Own end-to-end physical implementation of memory-centric computing IP and SoC partitions from RTL netlist through GDSII. Drive PPA convergence, timing closure, floorplanning, power delivery, placement, CTS, routing, STA, physical verification, and signoff on advanced process nodes. Collaborate with RTL, verification, foundry, and library teams while automating implementation flows with Tcl, Python, Perl, and AI tools.

Build and maintain large-scale hardware emulation and FPGA prototyping platforms for memory-centric computing SoCs. Partition complex ASIC/SoC designs, develop transactors and SCE-MI co-emulation environments, model memory and I/O interfaces, enable pre-silicon firmware and software bring-up, and run AI/ML workloads. Automate emulation flows, debug hardware and software issues, optimize platform trade-offs, and collaborate with engineering stakeholders to deliver validated designs.

Leads technical marketing and customer-facing design-in activities for semiconductor SoC products, including connectivity, modem, processor, and platform solutions. Manages customer accounts and programs, coordinates engineering, sales, and marketing teams, translates customer requirements into technical solutions, resolves issues, reports to executives, conducts market research, and develops strategic customer relationships across US and global teams.

Develops RTL and HLS IP for memory-centric computing systems supporting AI/ML workloads. Responsibilities include optimizing performance, power, and area; designing memory controllers, NOC, and interconnect IP; collaborating on verification and test plans; debugging hardware; making architecture trade-offs; and supporting SOC integration and stakeholder delivery.

Research and develop next-generation embedded memory firmware and architectures. Design, code, validate, and fine-tune firmware; perform lab bring-up and server integration; validate hardware IPs in virtual environments; develop HAL APIs and RTOS-based embedded memory software. Collaborate with cross-functional teams, customers, and partners throughout development and integration.

Build and operate representative LLM and distributed AI environments, collect traces and telemetry, develop benchmarks, and identify performance bottlenecks across compute, memory, interconnect, and scheduling. Profile and optimize workloads on NVIDIA GPU platforms, analyze large-scale distributed AI performance, and collaborate with hardware and software teams to guide hardware-software co-design for next-generation AI platforms.

Develop black-box functional test coverage and methodologies for NVMe SSDs; debug and triage failures with firmware teams; reproduce problems, design and run experiments; analyze customer field issues and improve functional test coverage.

Lead SoC integration efforts including reviewing and integrating third-party IPs (ARM, DDR, UCIe, Ethernet) with system bus, peripherals and CPU cores. Collaborate with architects, verification and physical design teams on synthesis, timing constraints, DFT insertion, lint/CDC checks, and static timing analysis to prepare designs for tape-out.

Lead end-to-end design of high-performance, low-power SRAM circuits for advanced process nodes. Responsibilities include bitcell, sense amp, decoder and control circuit design, PPA optimization, custom layout and DRC/LVS verification, simulation and variation analysis, automation scripting, silicon bring-up support, mentoring junior engineers, and contributing to SRAM methodology and IP development.

Lead Samsung foundry customer programs across process technologies, serving as primary technical account interface. Drive business growth, coordinate NPI to production with internal teams, ensure customer satisfaction, and achieve manufacturing milestones.

Provide high-level administrative support to management: manage schedules, coordinate meetings and events, collect and analyze information for decision-making, maintain office environment, and secure internal/external data. Require daily onsite presence in San Jose, CA and adherence to company policies and procedures.

Lead technical engagements with customers and ASIC partners to define silicon technology and platform requirements, identify gaps, and drive solutions across process, IP, packaging, design enablement, and ASIC teams. Perform PPA analysis and competitive benchmarking, influence technology roadmaps, support business development, publish technical analyses, and coordinate cross-functional teams to deliver customer-focused silicon solutions.

Drive product and go-to-market strategy for Samsung's Server SSD segment in North America. Perform market and competitive analysis, build customer/segment strategies, enable sales and design wins, create collateral and trainings, collaborate with technical teams and partners, and travel to customer sites to align product offerings with market needs.

Lead foundry market modelling, competitive sensing, and strategic analysis to support mid- and long-term business strategy. Build forecasting and demand models, analyze competitors and macro/micro trends, craft executive-level narratives and presentations, collaborate with sales and account teams, and establish processes and systems for market intelligence.

Lead strategy and execution for OCP S.A.F.E. certification across SSD product generations. Manage SRP vendors, coordinate cross-functional engineering and business stakeholders, track certification status, unblock issues, drive process improvements, and represent the security team in customer and industry forums.

Lead architecture and circuits for high-speed interconnect transceiver designs. Supervise designers and support silicon validation. Utilize low-power, low-voltage analog components.

The role involves managing AI related memory sales, negotiating agreements, ensuring customer satisfaction, optimizing supply chain activities, and aligning sales forecasts with production. Requires customer relationship building and frequent travel.

Design and productionize agentic multimodal AI applications and multi-agent systems; architect orchestration, routing, state/memory, and human-in-the-loop workflows; build evaluation and benchmarking frameworks; optimize inference on accelerated hardware (quantization, batching, runtime tuning); profile and solve AI acceleration and memory bottlenecks; collaborate with researchers and developers to deploy and operate large-scale LLM/vision systems.

The role involves researching AI system architecture, developing performance models, analyzing AI workloads, and guiding design decisions while collaborating across teams.