Jobs at Samsung Semiconductor, Inc.

Develops large-scale interactive web-based visual analytics and profiling tools for AI/ML workloads. Builds visualizations for massive telemetry datasets, partners with compiler and hardware teams, and improves workflows for diagnosing machine learning performance bottlenecks. The role requires extensive experience with data visualization, developer tools, profiling systems, computing architectures, and technical user experience design.

Executes enterprise SSD qualification testing in customer systems, coordinates test plans with internal and customer engineers, investigates failures, performs root-cause experiments, verifies fixes, supports field issue resolution, improves test coverage, and identifies automation opportunities. The role requires system-level testing or development experience with enterprise servers and storage, storage protocol expertise, server debugging, performance analysis, and scripting.

Design and validate high-speed SerDes transceiver architectures and analog circuits using advanced CMOS processes. Responsibilities include schematic development, simulation testbench creation, power and reliability optimization, supervision of layout designers, LVS/DRC validation, and silicon performance validation. The role focuses on low-power, high-speed interconnects for display, camera, UCIe, Ethernet, and related interfaces.

Designs RF/analog PLLs, clock-generation circuits, and SerDes analog PHYs in advanced CMOS technologies. Responsibilities include mixed-signal system modeling, circuit-level verification, production support, collaboration with digital and software teams, critical layout, and prototype lab testing. The role requires extensive experience with frequency synthesizers, PLL subsystems, IC design tools, hardware description languages, physical layout, and laboratory evaluation.

The Associate Manager, Public Relations will lead U.S. media relations, develop earned-media strategies, build journalist relationships, pitch stories, coordinate press events and launches, and support crisis communications. The role partners with internal teams to maintain consistent messaging, tracks media coverage and campaign performance, prepares reports for senior management, and advances brand awareness and business objectives. Daily onsite presence in San Jose, California is required.

Supports sales representatives, headquarters, and customers by managing orders, pricing, shipments, accounts receivable, credit issues, RMAs, samples, invoices, and customer returns. Aggregates sales forecasts for demand planning, enters and invoices orders through SAP, coordinates with logistics and warehouses, resolves discrepancies, and prepares management reports. The role requires daily onsite presence in San Diego, California.

Design and develop high-performance PLL and clock-generation circuits for RF transceivers, SerDes, and high-speed I/O applications. Responsibilities include PLL building-block design, system modeling, noise and jitter analysis, transistor-level verification, silicon correlation, mixed-signal calibration logic, critical layout guidance, and laboratory characterization of silicon prototypes.

Leads memory market intelligence by building analyst and partner networks, gathering market signals, analyzing supply and demand trends, developing scenario models, and translating findings into executive-ready narratives. Partners with sales and marketing teams across AI, server infrastructure, PC, and consumer markets. Uses AI tools to synthesize multi-source data and tracks market share, pricing, and inventory trends. Requires substantial semiconductor industry experience and daily onsite work in San Jose.

Leads SSD enablement, qualification, validation, and production readiness for NVIDIA, AMD, and other AI platforms. Coordinates customer and internal engineering teams to resolve hardware, firmware, PCIe/NVMe, thermal, power, performance, and interoperability issues. Identifies emerging AI storage workloads, conducts feasibility studies and proof-of-concepts, evaluates ecosystem trends, and develops future product opportunities.

Leads storage industry standardization across NVMe, NVMe-oF, OCP, and SNIA; influences committees, drafts specifications, develops patents, and aligns hyperscaler requirements with Samsung SSD controller and firmware roadmaps. The role collaborates with cloud providers and internal R&D, monitors competitive standards activity, supports compliance testing, and produces customer-facing technical education materials.

Lead Samsung’s enterprise and datacenter storage technology roadmap by influencing NVMe, OCP, and SNIA standards. Draft technical specifications, represent Samsung in industry committees, secure patents, translate hyperscaler requirements into SSD controller and firmware features, and align internal R&D with compliance and product goals. Collaborate with major cloud providers on next-generation storage architectures, monitor competitors, and develop technical marketing and customer education materials.

Leads foundry sales growth by generating new accounts, managing customer relationships through onboarding, developing semiconductor solutions, coordinating technical pitches and RFI/RFQ responses, negotiating contracts, and overseeing sales operations. The role requires deep logic foundry and semiconductor industry expertise, complex deal-closing experience, executive relationship management, and cross-functional leadership across global teams.

Drive SSD business growth in AI infrastructure, NeoCloud, and software-defined storage markets. Build technical relationships with customers, analyze storage architectures, translate workloads into SSD requirements, and lead technical discussions, proofs of concept, evaluations, qualification, and design-ins. Collaborate with R&D, product marketing, sales, and application engineering to shape product roadmaps, develop business cases, monitor market trends, and identify strategic opportunities.

Own Samsung’s OPC modeling products by defining product specifications, descriptions, qualification criteria, and feature goals. Partner with R&D and headquarters product engineers on new development, technical requirements, support, acceptance testing, best practices, user guidance, and manuals. The role requires semiconductor and lithography expertise, programming and debugging skills, and daily onsite work in San Jose.

Develop and optimize trace-driven power and thermal simulation engines, integrate IP-level power macromodels into system-level flows, manage time-indexed simulations across power and thermal domains, generate transient power maps and spatiotemporal hotspot analysis, interface with reduced-order thermal models and CFD-calibrated solvers, and ensure simulation performance, scalability, and reproducibility.

Manage customer design-in, qualification, technical enablement, and relationship development for Samsung DRAM products, including DDR, LPDDR, and HBM. Support SI/PI and timing analysis, self-qualification, PCN management, technical reviews, roadmap alignment, and customer debugging. Coordinate with Samsung headquarters and internal business teams to resolve technical and operational issues, influence supplier selection, and drive customer programs to closure. The role requires extensive semiconductor and DRAM experience, customer-facing technical expertise, Korean and English fluency, and occasional domestic and international travel.

Manage customer quality for advanced DRAM products supporting Tier 1 customers. Coordinate failure analysis, 8D responses, change notifications, performance reporting, issue tracking, and technical communications across customers and global engineering teams. Align quality requirements, manage response expectations, escalate issues, and drive sustainable solutions. The role requires semiconductor memory expertise, strong technical communication, customer-facing experience, and daily onsite work in San Jose with 20–30% travel.

Develops, acquires, and grows semiconductor foundry accounts from initial contact through onboarding. Leads account management, customer solutions, marketing pitches, RFQs, design awards, contract negotiations, and sales operations. Partners with Marketing, Finance, Legal, and global headquarters teams while translating semiconductor process capabilities into customer solutions. Requires extensive semiconductor industry experience, a strong executive network, and a proven record closing complex business development and sales deals.

Leads SoC architecture, microarchitecture, top-level integration, RTL implementation, and quality checks through ASIC tape-out. Reviews and integrates commercial IP including ARM, DDR, and UCIe components; collaborates with architects, verification, and physical design teams on synthesis, timing constraints, DFT, and static timing analysis. Supports ATE vector generation, testing, and silicon bring-up while balancing performance, power, and area.

Design and optimize ML compilers for high-performance deep learning applications across varied hardware platforms. Build staged lowering infrastructure, improve data locality and energy efficiency, integrate compiler features with hardware architectures, and collaborate with cross-functional engineering teams. Troubleshoot compiler issues, support customers, document solutions, and research emerging ML compiler and hardware technologies.