Search the 33 jobs at Rivos

Positions are open for a full-time SOC Emulation Engineer to work on developing Emulation and FPGA-based prototyping systems for SOC projects. Responsibilities include creating and supporting emulation models, driving SOC bringup, developing compile and runtime flows, working with tool vendors, and contributing to methodology and automation improvements.

The role involves leading design verification for AMS designs including components like droop sensing and PLL. Responsibilities include creating UVM benches, writing assertions, analyzing verification coverage, and collaborating with various teams to achieve complete verification.

As a Logic Equivalence Check Engineer, you will build and automate the verification flow, improve logical equivalent check processes, collaborate with design teams, and maintain CAD tools while debugging issues with verification tools.

As a Logic Equivalence Check Engineer, you'll develop and enhance the logical equivalence verification flow, collaborate with multiple design teams, resolve tool debugging issues, and maintain in-house CAD tools. You'll leverage your experience with logical equivalence tools and contribute to innovative solutions within the team.

The role involves analyzing workload performance, developing performance models, and validating performance in both pre-silicon and post-silicon stages. Collaboration with software engineers and hardware architects is essential to innovate and improve system performance in the rapidly evolving AI field.

The role involves developing innovative test generation strategies for an accelerator design, collaborating with software and hardware teams to create and improve test vectors, and profiling test generation code. The position requires strong problem-solving skills and the ability to work in a fast-paced team environment.

The Senior Memory Design Engineer will lead the design and development of custom SRAM and register file memories, optimizing for performance and power consumption while collaborating with other teams for circuit performance, simulation, and implementation. Responsibilities include conducting PPA analysis, design checks, working with mask designers, and delivering high-quality design collateral.

The role involves silicon design verification, developing tests to ensure functional correctness using assembly, C/C++, and SystemVerilog. Responsibilities include writing assertions, creating a test bench, investigating test failures, and enhancing verification workflows. The position requires collaboration with various engineering teams.

As an FPGA Design Engineer, you will design and implement FPGA RTL, build verification environments, and debug FPGAs and systems. This role offers the chance to expand into firmware development and requires teamwork and problem-solving skills.

As a Memory Controller Verification Engineer, you'll verify the digital logic aspects of DDR and HBM memory subsystems, develop test plans and testbenches, integrate verification IPs, and collaborate with design teams and third-party vendors. You'll also engage in debugging and regression activities, ensuring robust memory interface performance.

The Silicon Physical Design Verification Manager will develop PDV methodology and infrastructure for verifying large SoCs, ensuring quality integration across design teams and driving convergence at both full chip and sub-block levels, while managing a team of engineers to meet project milestones.

Seeking a Senior Memory Design Engineer to develop custom SRAM memories, Register file memories, and compiled memories, optimize power and performance metrics, and support silicon bring up. Responsibilities involve circuit design, simulation, equivalence checking, PPA analysis, and collaboration with cross-functional teams.

Seeking experienced UPF experts to build and validate IP/SOC level power intent definitions for high performance power efficient SOC designs. Responsible for bringing up power intent checking flows, debugging issues, and optimizing for low power. Requires strong communication, interpersonal skills, and scripting abilities in Tcl and Python.

Seeking a Senior Memory Design Engineer with 10 years of custom circuit design experience to drive the design and development of SRAM, register file, and custom cells for high performance and low power designs. Responsibilities include working with microarchitecture team, conducting PPA analysis, design equivalence checking, collaborating with CPU and SoC physical design teams, and interacting with technology and CAD teams.

Seeking a Senior Memory Design Engineer to develop custom SRAM memories, Register file memories, and compiled memories. Responsibilities include driving the design and development of custom cells for high performance and low power designs, conducting PPA analysis, equivalence checking, collaborating with various teams, and delivering high-quality design collateral.

Positions are open for full-time in the areas of DFT design from unit level to chip level, involving all aspects of DFT design functions from scan, MBIST, to ATPG. Roles in the areas of CPU and SOC DFT design and verification.

The Senior Memory Design Engineer will develop custom SRAM and register file memories to enhance circuit performance while optimizing power. Responsibilities include designing custom circuits, conducting PPA analysis, collaborating with various teams for design implementation, and ensuring high-quality design collateral. A solid background in circuit design and low power techniques is essential.

As a Post-Silicon Power Engineer, you will analyze workloads and their power dissipation, measure silicon power dissipation, improve power/performance ratios, and collaborate with cross-functional teams. Responsibilities include conducting power measurements and debugging system-level performance.

The Senior Memory Design Engineer will develop custom SRAM and register file memories while optimizing performance and power. Responsibilities include circuit design from scratch, working with the microarchitecture team, conducting sizing estimates, collaborating with various teams, and ensuring quality in design collateral.

The DFT Engineer role involves defining strategies for DFT design, creating test structures, and collaborating with various teams to ensure compliance with DFT requirements. Responsibilities also include validating designs, designing DFT features, and debugging.