Design and validate power systems for chip boards, collaborate with teams to ensure electrical and thermal requirements are met, and conduct testing and debugging.

The Senior Memory Design Engineer will develop custom SRAM and register file memories, focusing on performance and low power design while collaborating with various teams.

Analyze and improve performance for deep learning workloads, develop analytical models, and validate performance for AI computing platforms.

Perform post-silicon power activities including power validation, workload analysis, and cross-functional collaboration to optimize power performance ratios.

Develop state of the art custom SRAM and register file memories, focusing on circuit performance, low power design, and silicon bring up.

The DFT Engineer will design DFT features, develop strategies, validate requirements, and collaborate with teams on test coverage and debug observability.

The DFT Engineer will define DFT strategy, design DFT features, validate requirements, and collaborate with teams to ensure effective test coverage and debug observability.

Develop custom SRAM and register file memories for enhanced performance and low power designs, collaborating with various teams and ensuring quality deliverables.

Develop and design custom SRAM and register file memories, optimize circuit performance, and support silicon bring-up efforts. Engage with various teams to ensure high-quality designs.

Develop and debug emulation models and FPGA-based prototyping systems for SOC projects, collaborating with architecture and verification teams.

The Field Application Engineer supports integration of GPGPU and CPU designs into hardware, assists in customer training, and provides technical guidance.

The role involves developing and optimizing Deep Learning operator libraries and collaborating with cross-functional teams to enhance performance and efficiency of neural networks.

As an FPGA Design Engineer, you will develop and verify FPGA designs, implement RTL across platforms, and assist in lab testing and debugging.

Develop advanced test generation strategies to validate accelerator design performance. Collaborate with teams, profile code, and debug testing issues.

The LEC Engineer will develop automation for formal verification flows and collaborate with design teams to optimize solutions and tool debugging.

Design and develop custom SRAM memories and circuits, optimizing performance and power with extensive transistor level design experience.

Responsible for developing custom SRAM and register file memories, enhancing circuit performance, optimizing power, and collaborating across teams.

Responsible for building and automating formal verification flows, collaborating with design teams, and improving logical equivalence check processes.

Lead the design of analog blocks for advanced mixed-signal circuits, collaborating with architects and verification engineers, and managing vendor relations.

The intern will assist in CPU and SOC verification, develop test plans, write tests in assembly or C/C++, and conduct formal verification.