The role involves designing cache microarchitecture, developing RTL designs, collaborating on physical designs, and validating performance metrics.

As an Accelerator Microarchitecture Performance Modeling Engineer, you will develop simulators, analyze performance, and explore design choices for programming accelerators, primarily in the machine learning domain.

The role involves measuring, analyzing, and improving the power and performance of deep learning workloads using both software and hardware backgrounds, requiring experience with simulators, benchmarking, and coding in various programming languages.

Work on CPU and SOC verification at various levels, develop tests, analyze coverage, and assist in automation and regressions.

As a DFT Intern, you will design DFT features, create test vectors, validate requirements, and collaborate with teams for CPU and SOC DFT design and verification.

The intern will engage in CPU and SOC microarchitecture and logic design, focusing on RTL design, validation, and performance exploration.

The intern will work with designers on SOC verification, developing tests, analyzing coverage, and debugging simulations.

As an AMS Intern, you will design, simulate, and analyze analog circuits, assist in test planning, and support the tapeout process while collaborating with senior engineers and cross-functional teams.

This internship involves hands-on experience in the architecture, design, and verification of complex Risc-V based chips in a hardware startup.

The intern will work on SOC-level performance improvement through memory management innovations, collaborating with software and silicon teams on LLM workloads.

Interns will handle block-level design tasks including RTL-to-GDSII transitions, timing closure, and collaborate with engineers on methodologies and design validation.

The intern will participate in physical design tasks, including block level design, synthesis, timing closure, and collaborating with engineers to optimize PPA.

The intern will develop silicon interposer design flows, create unit cells, automate routing, and work with EDA tools and silicon manufacturers.

Interns will support CPU RTL design and verification tasks, including microarchitecture development, RTL design refinement, and functional validation.

The intern will assist in formal verification of a RISC-V core and accelerator designs, developing models, and verifying properties.

As a Performance Modeling intern, you will engage in microarchitecture research, workload analysis, software optimization, and tool development for system performance.

Leading the design of advanced analog blocks, collaborating on specifications, modeling, verification, and integration for high-performance computing technologies.

The role involves developing high-performance runtime libraries for GPGPU, collaborating with various teams to validate software with hardware, and extending tools for customers.

As a Senior Power-Management Architect, you will model and optimize power/performance features, define management features, and collaborate with teams for implementation and analysis.

Lead the design of analog circuits for advanced systems, ensuring development and verification of silicon IPs, while collaborating closely with various engineering teams.