Search the 32 jobs at Rivos

Open position for AI Software development at a fast-moving startup. Responsibilities include building components of an AI Software Stack, porting AI Software to run on a new hardware platform, profiling and tuning AI applications, implementing math operators used in AI, and building infrastructure to validate AI models. Required education includes Bachelor’s, Master’s, or PhD in Computer Engineering, Software Engineering or Computer Science. Optional requirements include experience with various AI frameworks, languages, and technologies. Strong problem-solving skills, communication skills, and self-motivation are essential. Ability to work well in a team and willingness to learn new skills are preferred. About the company: Rivos is focused on building industry-leading power efficient, high performance, secure server solutions based on RISC-V. Founded in 2021, Rivos has a world-class team and is backed by premier investors who share its vision.

Rivos is on a mission to build the best enterprise SOCs in the world with class leading performance, power, security and RAS features. We are seeking Memory Controller design verification engineers to join our team in building the best high performance memory interface in the world.

As a memory subsystem design verification engineer, you'll be responsible for all aspects of digital verification such as functional, performanc...

Join a hardware startup in Silicon Valley as a Junior Power-Management Architect focusing on modeling and optimizing Power/Performance features. Work with talented engineers to create designs for Accelerated computing platforms. Responsibilities include developing power management verification platform, collaborating with FW and SW teams, simulation, prototype validation, and more. BS/MS in CS/CE/EE required with 2-4 years of experience for BS and up to 2 years for MS. Strong programming skills and ability to work collaboratively in a dynamic environment.

Join a well-funded startup as an analog engineer leading the designs for various analog blocks and mixed-signal circuits using the latest technology nodes. Responsibilities include spec development, collaboration with cross-functional teams, design verification, and vendor management. Requires strong experience in silicon IP development, analog design techniques, and lab characterization.

Seeking a Software Engineer to work on optimizing communication collectives libraries for distributed systems in the AI ecosystem. Responsibilities include designing and implementing communication components, profiling and tuning AI applications' communications, and collaborating with hardware and software teams. Requires strong GPU architecture understanding, experience in parallel and distributed algorithms, and proficiency in communication collectives libraries like UCC and NCCL.

Positions are open for a full-time SOC Emulation Engineer to work on developing Emulation and FPGA-based prototyping systems for SOC projects. Responsibilities include creating and supporting emulation models, driving SOC bringup, developing compile and runtime flows, working with tool vendors, and contributing to methodology and automation improvements.

As an FPGA Design Engineer, you will be responsible for building up FPGA design and verification environments, implementing FPGA RTL, lab testing and debugging, and potentially expanding into firmware development. This role requires a strong foundation in FPGA design, operating systems, and circuit theory.

Join a cutting-edge hardware startup in Silicon Valley as a Multi-Chiplet Fabric Performance Engineer. Work on maximizing compute on each socket using chiplets and ensuring low latency and high bandwidth paths to system memory. Collaborate with talented engineers to design high-performance computing platforms. Enjoy a fun and creative work environment with a shared vision to create products that change the world.

Seeking experienced UPF experts to build and validate IP/SOC level power intent definitions for high performance power efficient SOC designs. Role involves interfacing with all disciplines to impact product marketability.

Responsible for architecture specification for external interfaces and their performance and power requirements. Working on Ethernet and PCIe/CXL subsystems for Datacenter products, collaborating with various teams within the company and industry consortiums.

Seeking a Post-Silicon Power Engineer to engage in power hardware validation and analysis of server compute silicon workloads. Responsibilities include power optimization, silicon power measurements, collaboration with cross-functional teams, and system level power & performance debug.

Join a cutting-edge hardware startup in Silicon Valley as a Deep Learning and Large Language Model Performance Architect. Responsibilities include workload analysis, performance modeling, and pre/post-silicon performance validation. Qualifications require an MS or PhD in CS, EE, or Math, in-depth knowledge of deep learning models, strong programming skills, and experience with computer architecture or AI software stack.

Develop cutting-edge test generation strategies for validating the performance and functionality of accelerator design. Collaborate with hardware and software teams to build code and explore architecture in novel ways. Profile, tune, and debug test generation code to enhance performance. Bachelor's, Master's, or PhD in Computer Science, Electrical Engineering, or related field required.

Join a hardware startup in Silicon Valley as a Silicon PDV Engineering Manager responsible for developing PDV methodology, driving convergence, performing full chip integration, and managing a team of engineers. Must have deep understanding of advanced process nodes, experience in full chip convergence for high-end chip designs, and strong scripting skills in tcl and python.

Seeking a Senior Memory Design Engineer to develop custom SRAM memories, Register file memories, and compiled memories, optimize power and performance metrics, and support silicon bring up. Responsibilities involve circuit design, simulation, equivalence checking, PPA analysis, and collaboration with cross-functional teams.

Responsible for internal interconnect architecture specification and performance optimization. Collaborate with Silicon team members and industry consortiums. Develop, assess, and refine architecture to meet power, performance, and timing goals.

Seeking experienced UPF experts to build and validate IP/SOC level power intent definitions for high performance power efficient SOC designs. Responsible for bringing up power intent checking flows, debugging issues, and optimizing for low power. Requires strong communication, interpersonal skills, and scripting abilities in Tcl and Python.

Develop PDV methodology and infrastructure for large SoCs, drive convergence at full chip level, work with internal and external design teams, manage team of engineers for PDV convergence.

As a Sr. ATE test engineer, responsible for test, characterization, and HVM shipment of Silicon. Develop production, qualification, and characterization test programs. In charge of test pattern conversion, hardware bring-up, and first-Si test pattern bring-up. Define test requirements, drive ATE to System level correlation, work on failure analysis, and debug during NPI phase. Require 10-12 years of ATE experience, strong hardware design understanding, hands-on experience with ATE test equipment, team leadership experience, and DfT experience. Bachelor's or Master's Degree in technical subject area.

Seeking a Senior Memory Design Engineer with 8-10 years of experience in custom circuit design, SRAM memories, Register file memories, SRAM compilers, and low power design techniques. Responsibilities include driving the design and development of custom circuits, working with microarchitecture team, conducting PPA analysis, equivalence checking, collaborating with CPU and SoC teams, and interacting with technology and CAD teams.