Search the 33 jobs at Rivos

As a Logic Equivalence Check Engineer, you'll develop and enhance the logical equivalence verification flow, collaborate with multiple design teams, resolve tool debugging issues, and maintain in-house CAD tools. You'll leverage your experience with logical equivalence tools and contribute to innovative solutions within the team.

As a Logic Equivalence Check Engineer, you will build and automate the verification flow, improve logical equivalent check processes, collaborate with design teams, and maintain CAD tools while debugging issues with verification tools.

As a Logic Equivalence Check Engineer, you will develop and enhance the logical equivalence verification flow, debug using ABORT/NEQ methods, work with logical equivalence tools, and maintain CAD tools. You'll collaborate with various engineering teams and vendors to create effective custom solutions, pushing the boundaries of performance and efficiency.

The role involves silicon design verification, developing tests to ensure functional correctness using assembly, C/C++, and SystemVerilog. Responsibilities include writing assertions, creating a test bench, investigating test failures, and enhancing verification workflows. The position requires collaboration with various engineering teams.

The AI Software Engineer will develop components of an AI software stack, optimize applications, implement mathematical operators, and validate models on new hardware platforms. The role requires collaboration and a strong desire to learn new skills.

The Global Supply Chain Manager will oversee sourcing and logistics operations, develop strategies for supplier partnerships, manage procurement and inventory, coordinate delivery schedules, and implement operational systems for efficiency. Collaboration with technical teams and suppliers is essential to ensure timely production and high-quality supply chain management.

The role involves leading the design of analog blocks for advanced mixed-signal circuits, writing detailed specifications, collaborating with architects and designers, verifying designs to ensure silicon quality, and managing vendor relationships.

The Multi-Chiplet Fabric Performance Engineer will define multi-chiplet interconnection solutions, create performance models for bandwidth estimation, and debug performance issues. This role involves collaborative work on architecture and implementation, ensuring the performance of RTL designs aligns with targets, while also developing tests for model quality.

As an FPGA Design Engineer, you will design and implement FPGA RTL, build verification environments, and debug FPGAs and systems. This role offers the chance to expand into firmware development and requires teamwork and problem-solving skills.

The UPF Engineer will develop and validate power intent definitions for SOC designs, focusing on power efficiency. Responsibilities include overseeing the entire RTL to GDS flow, ensuring power intent coverage, and collaborating with various teams to optimize power-aware simulations.

As a Memory Controller Verification Engineer, you'll verify the digital logic aspects of DDR and HBM memory subsystems, develop test plans and testbenches, integrate verification IPs, and collaborate with design teams and third-party vendors. You'll also engage in debugging and regression activities, ensuring robust memory interface performance.

The role involves analyzing workload performance, developing performance models, and validating performance in both pre-silicon and post-silicon stages. Collaboration with software engineers and hardware architects is essential to innovate and improve system performance in the rapidly evolving AI field.

The role involves developing innovative test generation strategies for an accelerator design, collaborating with software and hardware teams to create and improve test vectors, and profiling test generation code. The position requires strong problem-solving skills and the ability to work in a fast-paced team environment.

The Silicon Physical Design Verification Manager will develop PDV methodology and infrastructure for verifying large SoCs, ensuring quality integration across design teams and driving convergence at both full chip and sub-block levels, while managing a team of engineers to meet project milestones.

Seeking a Senior Memory Design Engineer to develop custom SRAM memories, Register file memories, and compiled memories, optimize power and performance metrics, and support silicon bring up. Responsibilities involve circuit design, simulation, equivalence checking, PPA analysis, and collaboration with cross-functional teams.

Responsible for internal interconnect architecture specification and performance optimization. Collaborate with Silicon team members and industry consortiums. Develop, assess, and refine architecture to meet power, performance, and timing goals.

Seeking experienced UPF experts to build and validate IP/SOC level power intent definitions for high performance power efficient SOC designs. Responsible for bringing up power intent checking flows, debugging issues, and optimizing for low power. Requires strong communication, interpersonal skills, and scripting abilities in Tcl and Python.

Develop PDV methodology and infrastructure for large SoCs, drive convergence at full chip level, work with internal and external design teams, manage team of engineers for PDV convergence.

Seeking a Senior Memory Design Engineer with 10 years of custom circuit design experience to drive the design and development of SRAM, register file, and custom cells for high performance and low power designs. Responsibilities include working with microarchitecture team, conducting PPA analysis, design equivalence checking, collaborating with CPU and SoC physical design teams, and interacting with technology and CAD teams.

Seeking a Senior Memory Design Engineer with 8-10 years of experience in custom circuit design, SRAM memories, Register file memories, SRAM compilers, and low power design techniques. Responsibilities include driving the design and development of custom circuits, working with microarchitecture team, conducting PPA analysis, equivalence checking, collaborating with CPU and SoC teams, and interacting with technology and CAD teams.