Jobs at Riverlane

Develop and integrate embedded software for quantum computing systems, configuring Deltaflow hardware and connecting it to customer quantum computers. Lead technical workshops, system deployments, benchmarking, troubleshooting, debugging, testing, documentation, and customer advocacy. Collaborate with quantum application, QA, hardware, and product teams to support quantum experiments and error-correction implementations. Mentor junior engineers while serving as a technical customer interface.

Supports Riverlane’s PMO across internal communications, event coordination, cross-team collaboration, knowledge management, tooling, process improvement, and operational support. The placement student will own workstreams, coordinate stakeholders, create resources, improve PMO processes, and solve practical business problems while working with Engineering, Science, Finance, Operations, and external vendors.

Design, develop, and test software supporting quantum error correction technology. Interns collaborate with software engineers, researchers, mathematicians, and physicists; evaluate technical approaches; solve problems; communicate findings; and build knowledge of quantum computing. The internship is full-time for 10–12 weeks in Cambridge, UK, and is intended for current technical students.

Work with hardware and software engineers on architectural optimizations for quantum error-correction decoders. The intern will enhance decoder flexibility and speed, evaluate design approaches, balance functionality, resources and performance, and communicate technical work through discussions, presentations and documentation. The role also involves developing knowledge of FPGA development, quantum computing and quantum error correction during a 10–12 week full-time internship.

Join Riverlane’s permanent engineering graduate scheme in Cambridge, rotating through engineering teams for 12 months. Design, develop, test, and improve software or hardware tools supporting quantum computing and quantum error correction. Collaborate with engineers and scientists, contribute to projects throughout the development lifecycle, and build technical skills through hands-on work and mentorship. Graduates will then move into an engineering or engineering research team.

Own and grow Riverlane’s Linux and HPC infrastructure, administering compute, storage, networking, Slurm scheduling, and RHEL systems. Responsibilities include troubleshooting, performance monitoring, security hardening, backup and disaster recovery, Synopsys EDA license management, automation with Bash, Python, and Ansible, infrastructure improvements, documentation, and technical support for HPC users.

Own the strategy and roadmap for a software product area in quantum computing and HPC. Engage customers, partners, and internal teams to understand market needs, prioritize features using product and competitive insights, align cross-functional stakeholders, identify opportunities, and support go-to-market launches. The role requires close collaboration with engineering, research, business development, marketing, and PMO teams, with quarterly travel under 10% of the time.

Manage Riverlane’s digital communications channels, social media, website content, newsletters, and integrated content calendar. Publish and promote company news, product updates, partnerships, events, and thought leadership. Support SEO and AI-search optimization, analyze channel performance, and use insights to improve audience engagement. Collaborate with Communications, Product Marketing, and Brand & Creative teams in a fast-paced technology environment.

Lead Riverlane’s open-source software strategy and oversee Deltakit, an open SDK supporting analysis tools, simulators, visualizers, and core components. Set technical priorities with product teams, guide development teams, support internal and global developer communities, and expand software adoption across the quantum ecosystem. The role requires leadership of complex open-source projects, strong Python and C++ skills, developer ecosystem experience, and knowledge of areas such as compilers, simulators, analysis tools, or programming languages.

Supports the commercial team through CRM hygiene, pipeline reporting, sales forecasting, contract and invoicing administration, meeting coordination, diary management, travel booking, and cross-functional communication. The role maintains accurate Salesforce and spreadsheet data, liaises with Finance, Legal, PMO, and global teams, and helps coordinate meetings, events, and customer-related activities.

Lead product marketing for Deltakit, Riverlane’s open-source SDK for quantum error correction. Develop positioning, messaging, go-to-market strategies, technical content, workshops, education programs, onboarding improvements, adoption metrics, and developer community growth. Partner closely with Product, Engineering, software teams, hardware customers, quantum computing companies, labs, and technical communities to increase platform adoption and support Deltaflow opportunities. Represent developer and user needs internally and travel globally to industry events approximately two to three times annually.

Develop research prototypes and production software for quantum error correction, including decoding algorithms, quantum simulation tools, and analysis systems. Collaborate with mathematicians, physicists, and engineers to create reliable, optimized, maintainable software. Contribute to the broader QEC stack, internal tools, and customer-facing implementations while applying software engineering best practices.

Lead the strategy and roadmap for Deltakit, an open-source QEC SDK. Engage users and partners, prioritise features, align cross-functional teams, support launches, drive developer adoption and community growth, and ensure strong documentation and onboarding.

Manage a portfolio of five to ten publicly funded R&D projects from grant award through final reporting. Responsibilities include maintaining plans, budgets, risks, resources, partner relationships, technical reports, financial claims, consortium activities, workshops, dependencies, and grant applications. The role requires translating scientific and engineering work into accurate funder documentation, coordinating cross-functional teams, and ensuring projects remain compliant and on schedule.

Lead technical development of DF-AMO, converting decoding research into a scalable, production-ready QEC software stack. Drive architecture, performance (latency/throughput) trade-offs, collaborate with engineering, research, product and customers, and mentor/manage a growing team of 5+ engineers to deliver from concept through deployment and adoption.

Lead design and implementation of a LLVM/MLIR-based compiler toolchain for error-corrected quantum computing. Build compilers, emulators, profilers, and debuggers; implement optimizations and IR transformations; own substantial parts of the software stack; mentor engineers; collaborate with hardware and science teams to integrate error-correcting codes and runtimes.

Design and build compilers, emulators, profilers and debuggers for error-corrected quantum systems. Implement QEC codes and runtimes, write maintainable code, collaborate with scientists and engineers, and deliver components of an LLVM MLIR-based compiler and runtime.

Lead development of Deltakit, turning QEC research into robust open-source software. Drive design, delivery, performance and scalability, mentor engineers, collaborate across teams, engage the research community, and run workshops to support adoption and shape technical direction.

Own end-to-end functional verification for block- and system-level designs. Define verification plans and strategies, build scalable SystemVerilog testbenches (UVM/OVM) with checkers, reference models, and SVA. Implement directed, random and self-testing, track regressions, coverage metrics and bugs, and debug across RTL, simulation and hardware. Collaborate with designers and architects to ensure high quality and reliability.

Lead FPGA integration for Riverlane's Deltaflow hardware: write RTL, implement and verify FPGA designs, benchmark latency, support on-site system deployments, debug with customers, and feed product improvements back to engineering and product teams.