Teams at Riverlane

Develop and extend classical simulation tools for fault-tolerant quantum computing and QEC, implement efficient techniques for Clifford and near-Clifford circuits, run numerical studies of logical operations and decoder performance, write code for scientific experiments, publish and present research, and collaborate across multidisciplinary teams and external partners.

Join Riverlane as a Graduate Verification Engineer to develop and execute verification plans for quantum error correction hardware. You'll create and run SystemVerilog/UVM testbenches, run simulations, debug with the design team, define verification strategies, and apply verification best practices. No prior quantum computing background required; learning on the job is supported.

Develop, optimise and maintain high-quality research software for quantum error correction. Implement reliable decoding algorithms, support simulation tooling, manage repositories and releases, collaborate with researchers, and mentor engineers; at staff level set technical direction and lead small teams.