Jobs at quadric.io

Drive customer evaluations to design wins for Quadric's Chimera GPNPU by porting and optimizing workloads, writing custom kernels, profiling and tuning performance, embedding with customer teams, and codifying reusable SDK skills and playbooks to accelerate future engagements.

Lead and build Quadric's marketing organization, owning brand, product marketing, demand generation, PR, developer marketing, events, and GTM. Translate complex hardware and AI technology into compelling narratives, run ABM and analytics, support product launches, manage agencies, and establish processes, metrics, and team to drive measurable business growth.

Lead architecture and build of a scratch SoC-level UVM verification environment. Develop test plans, directed and random drivers, and assembly/C++ tests. Verify complex SoC subsystems and 3rd-party IP (NoC, PCIe/UCIe, DDR) using VCS and Verilog/C co-simulation. Implement scalable testbenches, execute coverage-driven test suites, and communicate verification progress to cross-functional teams to achieve tapeout-ready coverage and HW/SW validation.

Lead SoC RTL design and integration across the full chip lifecycle: define SoC architecture, own subsystem development, integrate third-party IP (NoC, PCIe/UCIe, DDR, security), drive PPA optimization and timing closure, apply low-power techniques, package customer releases, and debug complex SW/HW interactions to deliver tapeout-ready designs.

Build cycle-level Python performance models of AI inference workloads for a novel GPNPU. Model tensor placement, tiling, memory hierarchy, sharding, and communication. Calibrate models against simulators and traces, analyze trade-offs (latency vs throughput), and produce technical studies that inform architecture and product decisions.

The AI Inference Engineer will port, optimize, and benchmark AI models for Quadric's platform while providing support and documentation.

The AI Kernel Engineer will develop and optimize AI kernels for Quadric's platform, enhancing performance across various hardware configurations and providing technical support.

The Design Verification Intern will assist in verifying CPU/GPU designs, collaborate on test plans, and debug tests. Familiarity with verification methodologies is required.

As a Deep Learning Compiler Engineer, you'll optimize neural networks for Quadric's architecture, focusing on algorithmic optimizations and collaboration with the software team.

As a Deep Learning Compiler Engineer, you will own compiler passes, debug compilation issues, collaborate with teams, and improve compiler performance for edge devices.

The AI Applications Engineer will lead technical support initiatives, develop demos and benchmarks, and provide customer training using Quadric's SDK. This role requires expertise in system architecture and optimization strategies, along with strong coding skills and the ability to troubleshoot complex issues.

As a Senior Deep Learning Compiler Engineer, you will optimize neural networks and develop algorithms for Quadric’s architecture, focusing on performance enhancement through advanced mathematical and algorithmic techniques.

As a Senior Hardware Engineer, you will define processor architecture, implement microarchitecture in SystemC/SystemVerilog, and optimize PPA across design cycles.

As a Senior Compiler Engineer, you will optimize the performance of code on Quadric processors, enhance LLVM compiler development, and collaborate with hardware teams for co-optimization.

The AI Kernel Engineer will develop and optimize AI kernels for inference on Quadric's platform, analyze performance bottlenecks, and improve toolchains.

The Full-Stack Engineer will implement features for a web platform, provide support, create documentation, and troubleshoot issues. Requires deep technical skills in building complex systems.

Lead end-to-end ISO 26262 functional safety certification for Quadric's NPU software stack, ensuring compiler (TVM/LLVM) and SDK compliance, defining safety processes, producing safety artifacts, qualifying tools, and supporting OEM/Tier-1 customers.

The Director/Sr Program Manager will oversee the program management of AI acceleration chips, ensuring timely software releases and compliance with safety standards. This role involves collaboration with cross-functional teams and customer advocacy.