Jobs at Powerlattice Inc

Lead digital and mixed-signal SoC verification from RTL through gate-level simulation. Responsibilities include architecting SystemVerilog and UVM environments, developing constrained-random tests, assertions, coverage, regression and GLS flows, debugging failures, verifying protocols and clock domains, driving coverage closure, and mentoring verification engineers. The role collaborates with RTL, analog, architecture, and silicon validation teams to resolve design issues and achieve verification signoff.

Lead laboratory evaluation and debugging of chiplet power converters for key customer accounts. Develop testing, identify root causes, document findings, create application notes and operating guides, support conference collateral, assist project scheduling, and guide team members in resolving customer issues. The role requires extensive integrated-circuit applications engineering experience, Python-based lab automation, electronics laboratory expertise, customer problem-solving, and silicon bring-up and post-silicon debugging.

Manage end-to-end semiconductor and hardware development programs from planning through production release. Coordinate ASIC/SoC design, verification, physical design, firmware, PCB development, validation, manufacturing, supply chain, and external vendors. Maintain schedules, milestones, dependencies, resources, and risk assessments; manage tape-out, package development, board bring-up, production readiness, issue escalation, and executive reporting. Drive cross-functional alignment and continuous improvement across geographically distributed teams.

Designs complex digital systems and SoC components from microarchitecture through RTL, integration, synthesis, timing closure, and implementation. Collaborates with verification, physical design, DFT, firmware, and systems teams; resolves design issues; supports silicon bring-up and post-silicon debug. The role also contributes to design quality, methodology improvement, and, at Staff level, mentoring junior engineers. It is a hybrid position requiring three days onsite in Vancouver, WA, or Chandler, AZ.

The role involves designing and developing analog and mixed-signal integrated circuits, conducting simulations, providing layout guidance, and supporting silicon validation.

The Senior/Staff Hardware Design Engineer will lead hardware design and system integration for AI/datacenter motherboard development, ensuring architectural alignment and performing rigorous analysis and optimization.