Jobs at Positron AI

Designs and implements Go-based control-plane software for custom AI inference hardware. Responsibilities span system management APIs, Linux services, hardware interfaces, diagnostics, observability, security, firmware updates, distributed systems, and workload management. The role requires hands-on debugging across application, operating system, firmware, and hardware boundaries, plus technical leadership, mentoring, architecture, and production ownership. Regular on-site lab work includes server racking, system bring-up, hardware troubleshooting, and documentation.

Own full-cycle recruiting for specialized hardware engineering roles, including ASIC, RTL, verification, physical design, DFT, and silicon validation. Partner with engineering leaders to define hiring needs, source passive candidates, manage interviews, close experienced engineers, and improve recruiting operations. Use pipeline data, recruiting tools, LLMs, and agentic AI to increase efficiency while maintaining human-centered candidate engagement.

Define multi-generation hardware/software architectures for AI inference silicon, including boot, memory, DMA, scheduling, security, telemetry, and host/device interfaces. Integrate firmware, Linux, runtimes, simulation, and developer tooling; lead architecture reviews; resolve cross-team technical issues; prototype high-risk interfaces; and mentor senior engineers. The role requires deep systems expertise, strong C or C++ skills, and architecture-level ownership across pre-silicon, silicon bring-up, and production software.

Lead power architecture, modeling, optimization, and verification for AI accelerators. Develop lifecycle power models, drive low-power techniques (clock/power gating, voltage islands), own UPF/CPF flows and power-aware verification, partner with cross-functional teams on power integrity and silicon validation, and apply AI tools to improve power analysis and anomaly detection.

Own synthesis, timing closure, constraint development, and implementation readiness for ASIC accelerator partitions. Execute Cadence Genus or Synopsys Design Compiler flows, develop SDC and MMMC environments, optimize timing, area, power, and congestion, and collaborate with RTL, verification, DFT, physical design, and backend teams. Improve synthesis methodology, analyze QoR and timing bottlenecks, support vendor partners, and apply AI tools to engineering automation and report analysis.

Leads microarchitecture, RTL implementation, and signoff for complex IP blocks and subsystems in AI inference ASICs and SoCs. Owns PPA optimization, interface and memory integration, lint, CDC/RDC, DFT, synthesis, and timing closure. Collaborates with architecture, verification, physical design, and vendors; develops design methodologies and automation; supports silicon bring-up and customer engagements; and mentors junior engineers while driving technical decisions.

Own end-to-end DFT architecture and implementation for AI accelerator ASICs, including scan, compression, ATPG, MBIST, boundary scan, IJTAG, verification, and physical-design integration. Drive pre-silicon coverage, timing and power-aware test implementation, silicon bring-up, and cross-functional execution through tapeout. The role requires hands-on RTL, synthesis, gate-level verification, Tessent tool expertise, scripting, and failure analysis across multiple production tapeouts.

Lead the microarchitecture, SystemVerilog RTL design, integration, optimization, and signoff of complex ASIC and SoC IP for AI inference hardware. Own PPA targets, interfaces, memory integration, verification collaboration, DFT, CDC/RDC, synthesis, timing closure, and post-silicon support. Establish design methodologies, mentor engineers, lead technical reviews, and drive cross-functional architectural decisions.

Build simulation and modeling infrastructure for AI inference accelerators before silicon availability. Develop analytical performance models, functional and timing simulators, virtual platforms, and software integrations. Validate functionality and performance against reference implementations and hardware, improve simulator speed and usability, and create automated regression coverage. Collaborate with hardware, compiler, firmware, runtime, performance, and test engineers to support architecture exploration and realistic software workloads.

Contribute to physical implementation of AI accelerator ASICs from floorplanning and macro placement through tapeout. Responsibilities include clock tree synthesis, place and route, timing, power, signal integrity, IR/EM, DRC, LVS, congestion, ECOs, metal fill, and signoff closure. The role also supports implementation methodology, advanced-node tapeouts, AI-enabled QoR analysis, and collaboration with RTL, synthesis, DFT, package, and backend teams.

Owns AI-assisted engineering across accelerator software teams, embedding agentic workflows into coding, debugging, triage, testing, documentation, CI, and silicon-debug processes. Builds shared agent tooling, maintains evaluations, measures productivity gains, and establishes standards for reliable AI-native development. Requires expert experience with Codex, Claude Code, LLM APIs, evaluations, and adopted developer tooling, plus strong systems or infrastructure credibility.

Lead the architecture, design, verification, physical implementation, tape-out, validation, and production ramp of high-performance AI inference ASICs. Drive PPA optimization, memory subsystem design, hardware/software co-design, and relationships with foundries, IP vendors, and EDA providers. Recruit and mentor the ASIC team while shaping the company’s silicon roadmap and execution methodology.

Owns synthesis methodology, timing closure, constraint development, QoR optimization, and implementation readiness for advanced AI accelerator ASICs. The role transforms RTL into implementation-ready netlists, leads physical-aware optimization and timing budgeting, collaborates across architecture, verification, DFT, and backend teams, and provides technical leadership to external implementation partners. Responsibilities also include developing Tcl and Python automation and applying AI to improve timing analysis, regression, debugging, and engineering workflows.

Develop and lead verification strategies for AI inference ASICs, including SystemVerilog UVM environments, simulation testbenches, directed and constrained-random testing, coverage closure, debugging, and root-cause analysis. Collaborate with design, architecture, software, FPGA, and emulation teams across pre-silicon and post-silicon validation. Manage verification schedules, deliverables, and risk mitigation while helping ensure functional correctness and performance.

Lead ASIC/SoC IP and subsystem development from microarchitecture through RTL signoff. Design parameterized SystemVerilog RTL, own PPA targets, and lead lint, CDC/RDC, DFT, synthesis, and timing activities. Architect interfaces, DMA, coherency, and HBM/DDR integration while collaborating with architecture, verification, and physical design teams. Improve design methodologies, mentor engineers, lead reviews, support post-silicon debug, and contribute automation flows.

The Senior Software Engineer will develop high-performance software for executing open-source LLMs on custom hardware, focusing on optimizations and efficient libraries primarily in C++.

Lead architecture and performance exploration for next-generation AI inference accelerators. Build analytical models and simulation frameworks, define subsystem interfaces and roadmaps, and drive hardware/software co-design with compiler, runtime, ML, and silicon teams to optimize latency, throughput, memory, interconnects, power, and cost for evolving LLMs and transformer-based workloads.

Lead pre-silicon emulation strategy for a next-generation AI inference ASIC using Cadence Palladium. Architect multi-rack models, enable software left-shift via hybrid emulation, verify high-speed interfaces and memory hierarchies, perform power/performance analysis, and collaborate with RTL, DV, software teams and Cadence R&D to ensure silicon readiness.