Teams at Positron AI

Define multi-generation hardware/software architectures for AI inference silicon, including boot, memory, DMA, scheduling, security, telemetry, and host/device interfaces. Integrate firmware, Linux, runtimes, simulation, and developer tooling; lead architecture reviews; resolve cross-team technical issues; prototype high-risk interfaces; and mentor senior engineers. The role requires deep systems expertise, strong C or C++ skills, and architecture-level ownership across pre-silicon, silicon bring-up, and production software.

Lead power architecture, modeling, optimization, and verification for AI accelerators. Develop lifecycle power models, drive low-power techniques (clock/power gating, voltage islands), own UPF/CPF flows and power-aware verification, partner with cross-functional teams on power integrity and silicon validation, and apply AI tools to improve power analysis and anomaly detection.

Own synthesis, timing closure, constraint development, and implementation readiness for ASIC accelerator partitions. Execute Cadence Genus or Synopsys Design Compiler flows, develop SDC and MMMC environments, optimize timing, area, power, and congestion, and collaborate with RTL, verification, DFT, physical design, and backend teams. Improve synthesis methodology, analyze QoR and timing bottlenecks, support vendor partners, and apply AI tools to engineering automation and report analysis.