Teams at Positron AI

Lead the architecture, design, verification, physical implementation, tape-out, bring-up, and production ramp of high-performance AI inference ASICs. Optimize power, performance, area, and memory subsystems while managing foundry, IP, and EDA vendor relationships. Partner with software and prototyping teams on hardware-software co-design, define the silicon roadmap, and recruit and mentor the ASIC engineering team.

Lead verification of AI inference ASICs by developing verification strategies, UVM environments, simulation testbenches, constrained-random tests, and coverage plans. Collaborate with architecture, design, software, FPGA, and emulation teams to debug issues, achieve functional coverage closure, validate hardware before and after silicon, and manage verification schedules and risks.

Own synthesis, timing closure, constraint development, and implementation readiness for AI accelerator ASIC partitions. Deliver high-quality netlists, optimize timing, area, power, congestion, and wireability, and collaborate with RTL, architecture, verification, DFT, physical design, and external implementation teams. Develop scalable synthesis methodologies, automate flows using Tcl and Python, support advanced-node designs, and provide physical-aware optimization and timing feedback.