Jobs at Phizenix

Lead design and verification of high-speed analog and mixed-signal circuits (ADCs, DACs, PLLs, TIAs, SerDes, optical drivers) through tape-out and post-silicon bring-up in advanced FinFET or SOI processes. Collaborate cross-functionally, create documentation, present to leadership, and mentor junior designers.

Manage ERP and subsidy management projects, oversee risks, issues, project charters, stakeholder engagement, and release cycles (semi-annual Workday releases). Ensure compliance with SOX/SDLC controls and coordinate with Agile Delivery Leads across Scrum and Kanban teams.

This role involves driving new client acquisition and revenue growth through full-cycle sales execution and relationship building with stakeholders, while maintaining pipeline tracking in CRM.

Lead RTL-to-GDSII implementation on advanced-node digital designs, driving PPA and quality-of-results. Own flows, debug complex issues, collaborate with CAD/design/program teams, mentor juniors, adopt new tools and ML techniques, and engage EDA vendors to resolve root causes.

Develop synthesizable RTL from micro-architecture, write bare-metal firmware for on-chip RISC CPUs, drive pre-silicon simulation and hardware-software co-verification, lead synthesis/timing closure and equivalence checking, build emulation environments, and perform silicon bring-up and post-silicon debug while collaborating across analog, verification, and physical-design teams.

Lead block-level physical design for analog/mixed-signal and high-speed interfaces (SerDes, PAM4). Own floorplanning, placement, routing, parasitic-aware layout, signoff checks (DRC/LVS/ERC/EM/IR), and top-level integration. Collaborate with designers, packaging, process, and product teams; support tapeout readiness, CAD automation, mentoring, and post-silicon debug to deliver manufacturable, high-performance IC layouts.

Senior individual contributor or technical lead designing and verifying high-speed analog and mixed-signal ICs (ADCs, DACs, PLLs, TIAs, laser/modulator drivers, SerDes). Drive transistor-level design and layout in advanced FinFET/SOI processes, lead pre-/post-silicon validation, collaborate with cross-functional teams, document results, and mentor junior designers.

Design and implement synthesizable RTL for high-speed interconnect ASICs, drive synthesis/timing closure, develop bare-metal firmware for embedded RISC CPU IP, lead pre-silicon simulation, emulation, and silicon bring-up, and collaborate across verification, physical-design, analog, and DSP teams to debug and integrate hardware-software systems.

Lead and execute analog/mixed-signal IC design for high-speed interconnects from architecture through tape-out and bring-up. Manage and mentor a design team, coordinate external contractors and IP vendors, design/verify SerDes front-ends, optical drivers, ADC/DACs, and transistor-level schematics in advanced FinFET/SOI nodes, drive pre-silicon simulation and post-silicon debug to meet PPA targets.

The role involves design verification of IP/SoC with hands-on experience in verification methodologies, particularly UVM/OVM, and requires strong problem-solving skills in a fast-paced environment.

Lead and execute migrations of mainframe application source control and DevOps pipelines to IBM tooling (DBB, Git, IDz, IDD). Perform conversion analysis, install/configure/troubleshoot migration tools, support build/branching/pipeline transitions, validate converted applications, and deliver customer training and technical presentations in z/OS/IBM Z environments.

Lead migrations of batch scheduling workloads to IBM Z Workload Scheduler by analyzing legacy scheduler definitions, mapping jobs and dependencies, executing parallel tracking and validation, monitoring execution via TSO/ISPF and scheduler interfaces, resolving issues, and training operational teams.

Lead and deliver IBM Z software migration projects: define scope, plans, timelines; manage resources, risks, change control, vendors, and stakeholder communications across multiple technical workstreams to ensure successful delivery.

Lead migrations of mainframe automation from CA OPS/MVS and CA Automation Point to IBM Systems Automation (Tivoli/SAIOM). Configure, install, and troubleshoot IBM Systems Automation for z/OS, develop REXX execs and PDB policies, collaborate with operations to improve startup, shutdown, recovery, and HA automation processes.

The Business Development Manager will focus on acquiring new clients and expanding accounts within the IT staffing sector, managing the full sales cycle and meeting revenue targets.

The Senior Staff DFT Engineer will architect and implement DFT/DFX solutions for AI accelerator SoCs, ensuring manufacturability and silicon debug, while collaborating across teams.

Responsible for designing and building automated test frameworks for AI hardware/software, focusing on validation of machine learning models and CI/CD processes.

Senior technology leader responsible for FP&A systems and engineering applications, driving large-scale global standardization and transformation. Oversees lab operations, program management, stakeholder alignment, and communication; brings semiconductor workflow and lab automation expertise.

Operate, automate, and ensure reliability of colocation, on-prem GPU clusters, and cloud environments. Build IaC (Terraform/Ansible), automation, monitoring (Prometheus/Grafana, DataDog), run on-call incident response, produce RCAs, and support customer-facing platform services and documentation.

Lead and build an SRE function for AI accelerator infrastructure across colocation, on-prem lab clusters, and multi-cloud. Hire and manage a small SRE team, define SLOs/SLIs, own observability and incident management, drive IaC and automation (Terraform/Ansible), manage storage and HPC integrations, and align reliability with DevOps and executive stakeholders.